gem5  v22.1.0.0
a2901_edge.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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21 
22  a2901_edge.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
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33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 #ifndef A2901_EDGE_H
39 #define A2901_EDGE_H
40 
41 #include "common.h"
42 
43 SC_MODULE( a2901_edge )
44 {
45  SC_HAS_PROCESS( a2901_edge );
46 
47  // clock
48  const sc_clock& CLK;
49 
50  // shared state
51  long* RAM;
52 
53  // inputs
54  const sig9& I;
55  const sig4& Badd;
56  const sig4& F;
57  const sig1& Q3;
58  const sig1& Q0;
59  const sig1& RAM3;
60  const sig1& RAM0;
61 
62  // outputs
63  sig4& Q;
64 
65  // temporaries
66  sc_uint<3> i86;
67  sc_uint<3> i87;
68  sc_uint<3> q31, q20;
69  sc_uint<3> f31, f20;
70 
71  // constructor
72  a2901_edge( sc_module_name,
73  const sc_clock& CLK_,
74  long* RAM_,
75  const sig9& I_,
76  const sig4& Badd_,
77  const sig4& F_,
78  const sig1& Q3_,
79  const sig1& Q0_,
80  const sig1& RAM3_,
81  const sig1& RAM0_,
82  sig4& Q_ )
83  : CLK( CLK_ ),
84  RAM( RAM_ ),
85  I( I_ ),
86  Badd( Badd_ ),
87  F( F_ ),
88  Q3( Q3_ ),
89  Q0( Q0_ ),
90  RAM3( RAM3_ ),
91  RAM0( RAM0_ ),
92  Q( Q_ )
93  {
94  SC_METHOD( entry );
95  sensitive << CLK.posedge_event();
96  }
97 
98  void entry();
99 };
100 
101 #endif
102 
SC_MODULE(a2901_edge)
Definition: a2901_edge.h:43
sc_signal< int1 > sig1
Definition: common.h:48
sc_signal< int9 > sig9
Definition: common.h:51
sc_signal< int4 > sig4
Definition: common.h:49
#define SC_METHOD(name)
Definition: sc_module.hh:303
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:301

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