gem5  v22.0.0.2
add_chain.h
Go to the documentation of this file.
1 /*****************************************************************************
2 
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements. See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License. You may obtain a copy of the License at
9 
10  http://www.apache.org/licenses/LICENSE-2.0
11 
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied. See the License for the specific language governing
16  permissions and limitations under the License.
17 
18  *****************************************************************************/
19 
20 /*****************************************************************************
21 
22  add_chain.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 #include "common.h"
39 
40 /******************************************************************************/
41 /*************************** add_chain Class Definition ********************/
42 /******************************************************************************/
43 
44 SC_MODULE( ADD_CHAIN )
45 {
46  SC_HAS_PROCESS( ADD_CHAIN );
47 
48  sc_in_clk clk;
49 
50  const sc_signal<bool>& rst;
51  const signal_bool_vector8& a_in;
52  signal_bool_vector4& sum_out;
53  sc_signal<bool>& ready;
54 
55  ADD_CHAIN( sc_module_name NAME,
56  sc_clock& TICK_P,
57 
58  const sc_signal<bool>& RST,
59  const signal_bool_vector8& A_IN,
60  signal_bool_vector4& SUM_OUT,
61  sc_signal<bool>& READY
62  )
63  :
64  rst (RST),
65  a_in (A_IN),
66  sum_out (SUM_OUT),
67  ready (READY)
68  {
69  clk(TICK_P);
70  SC_CTHREAD( entry, clk.pos() );
71  reset_signal_is(rst, false);
72  }
73  void entry();
74 };
75 
76 /******************************************************************************/
77 /*************************** add_chain Entry Function **********************/
78 /******************************************************************************/
82 /******************************************************************************/
83 void
84 ADD_CHAIN::entry()
85 {
87  bool_vector8 a;
88 
89  /***** Reset Initialization *****/
90  sum_out.write(0);
91  ready.write(1);
92  wait();
93 
94  /***** MAIN LOOP *****/
95  while(true) {
96 
97  /***** Handshake *****/
98  ready.write(0);
99  wait();
100 
101  /***** Computation *****/
102  sum = 0;
103  a = a_in.read();
104 
105  for (int i=0; i<=7; i=i+1) {
106  sum = sum.to_uint() + a[i].to_bool();
107  }
108 
109  sum_out.write(sum);
110 
111  /***** Handshake *****/
112  ready.write(1);
113  wait();
114  }
115 }
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:66
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
signal_bool_vector4
sc_signal< bool_vector4 > signal_bool_vector4
Definition: common.h:46
SC_MODULE
SC_MODULE(ADD_CHAIN)
Definition: add_chain.h:44
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
sc_core::wait
void wait()
Definition: sc_module.cc:653
bool_vector4
sc_bv< 4 > bool_vector4
Definition: common.h:44
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:301
bool_vector8
sc_bv< 8 > bool_vector8
Definition: common.h:45
common.h
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:323
gem5::RiscvISA::sum
Bitfield< 18 > sum
Definition: misc.hh:555
signal_bool_vector8
sc_signal< sc_bv< 8 > > signal_bool_vector8
Definition: common.h:43

Generated on Thu Jul 28 2022 13:32:42 for gem5 by doxygen 1.8.17