gem5  v21.2.1.1
isa.cc
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31 
33 
34 #include <numeric>
35 
37 #include "gpu-compute/wavefront.hh"
38 
39 namespace gem5
40 {
41 
42 namespace VegaISA
43 {
44  GPUISA::GPUISA(Wavefront &wf) : wavefront(wf), m0(0)
45  {
46  }
47 
49  GPUISA::readMiscReg(int opIdx) const
50  {
51  switch (opIdx) {
52  case REG_M0:
53  return m0;
54  case REG_ZERO:
55  return 0;
56  case REG_SCC:
57  return statusReg.SCC;
58  default:
59  fatal("attempting to read from unsupported or non-readable "
60  "register. selector val: %i\n", opIdx);
61  return 0;
62  }
63  }
64 
65  void
66  GPUISA::writeMiscReg(int opIdx, ScalarRegU32 operandVal)
67  {
68  switch (opIdx) {
69  case REG_M0:
70  m0 = operandVal;
71  break;
72  case REG_SCC:
73  statusReg.SCC = operandVal ? 1 : 0;
74  break;
75  default:
76  fatal("attempting to write to an unsupported or non-writable "
77  "register. selector val: %i\n", opIdx);
78  break;
79  }
80  }
81 
82  void
84  {
86  + gpuDynInst->staticInstruction()->instSize());
87  }
88 
89  const std::array<const ScalarRegU32, NumPosConstRegs>
91  1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
92  20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
93  37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
94  54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
95  } };
96 
97  const std::array<const ScalarRegI32, NumNegConstRegs>
99  -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15,
100  -16
101  } };
102 } // namespace VegaISA
103 } // namespace gem5
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::VegaISA::REG_SCC
@ REG_SCC
Definition: gpu_registers.hh:128
gem5::VegaISA::REG_M0
@ REG_M0
Definition: gpu_registers.hh:74
gem5::VegaISA::GPUISA::GPUISA
GPUISA(Wavefront &wf)
Definition: isa.cc:44
gem5::Wavefront
Definition: wavefront.hh:60
gpu_static_inst.hh
gem5::Wavefront::pc
Addr pc() const
Definition: wavefront.cc:1363
wavefront.hh
gem5::VegaISA::GPUISA::readMiscReg
ScalarRegU32 readMiscReg(int opIdx) const
Definition: isa.cc:49
gem5::VegaISA::GPUISA::statusReg
StatusReg statusReg
Definition: gpu_isa.hh:98
gem5::VegaISA::REG_ZERO
@ REG_ZERO
Definition: gpu_registers.hh:78
gem5::VegaISA::GPUISA::advancePC
void advancePC(GPUDynInstPtr gpuDynInst)
Definition: isa.cc:83
gem5::VegaISA::GPUISA::posConstRegs
static const std::array< const ScalarRegU32, NumPosConstRegs > posConstRegs
Definition: gpu_isa.hh:90
gem5::VegaISA::GPUISA::negConstRegs
static const std::array< const ScalarRegI32, NumNegConstRegs > negConstRegs
Definition: gpu_isa.hh:92
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49
gem5::VegaISA::GPUISA::writeMiscReg
void writeMiscReg(int opIdx, ScalarRegU32 operandVal)
Definition: isa.cc:66
gem5::VegaISA::GPUISA::wavefront
Wavefront & wavefront
Definition: gpu_isa.hh:95
gem5::VegaISA::ScalarRegU32
uint32_t ScalarRegU32
Definition: gpu_registers.hh:153
gem5::VegaISA::StatusReg::SCC
uint32_t SCC
Definition: gpu_registers.hh:194
gem5::VegaISA::GPUISA::m0
ScalarRegU32 m0
Definition: gpu_isa.hh:100
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gpu_isa.hh

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