gem5  v21.1.0.2
locked_mem.hh
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41 
42 #ifndef __ARCH_ARM_LOCKED_MEM_HH__
43 #define __ARCH_ARM_LOCKED_MEM_HH__
44 
51 #include "arch/arm/regs/misc.hh"
52 #include "arch/arm/utility.hh"
53 #include "debug/LLSC.hh"
54 #include "mem/packet.hh"
55 #include "mem/request.hh"
56 
57 namespace gem5
58 {
59 
60 namespace ArmISA
61 {
62 template <class XC>
63 inline void
64 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
65 {
66  // Should only every see invalidations / direct writes
67  assert(pkt->isInvalidate() || pkt->isWrite());
68 
69  DPRINTF(LLSC,"%s: handling snoop for address: %#x locked: %d\n",
70  xc->getCpuPtr()->name(),pkt->getAddr(),
71  xc->readMiscReg(MISCREG_LOCKFLAG));
72  if (!xc->readMiscReg(MISCREG_LOCKFLAG))
73  return;
74 
75  Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
76  // If no caches are attached, the snoop address always needs to be masked
77  Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
78 
79  DPRINTF(LLSC,"%s: handling snoop for address: %#x locked addr: %#x\n",
80  xc->getCpuPtr()->name(),snoop_addr, locked_addr);
81  if (locked_addr == snoop_addr) {
82  DPRINTF(LLSC,"%s: address match, clearing lock and signaling sev\n",
83  xc->getCpuPtr()->name());
84  xc->setMiscReg(MISCREG_LOCKFLAG, false);
85  // Implement ARMv8 WFE/SEV semantics
86  sendEvent(xc);
87  xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
88  }
89 }
90 
91 template <class XC>
92 inline void
93 handleLockedRead(XC *xc, const RequestPtr &req)
94 {
95  xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr());
96  xc->setMiscReg(MISCREG_LOCKFLAG, true);
97  DPRINTF(LLSC,"%s: Placing address %#x in monitor\n", xc->getCpuPtr()->name(),
98  req->getPaddr());
99 }
100 
101 template <class XC>
102 inline void
104 {
105  DPRINTF(LLSC,"%s: handling snoop lock hit address: %#x\n",
106  xc->getCpuPtr()->name(), xc->readMiscReg(MISCREG_LOCKADDR));
107  xc->setMiscReg(MISCREG_LOCKFLAG, false);
108  xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
109 }
110 
111 template <class XC>
112 inline bool
113 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
114 {
115  if (req->isSwap())
116  return true;
117 
118  DPRINTF(LLSC,"%s: handling locked write for address %#x in monitor\n",
119  xc->getCpuPtr()->name(), req->getPaddr());
120  // Verify that the lock flag is still set and the address
121  // is correct
122  bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
123  Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
124  if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) {
125  // Lock flag not set or addr mismatch in CPU;
126  // don't even bother sending to memory system
127  req->setExtraData(0);
128  xc->setMiscReg(MISCREG_LOCKFLAG, false);
129  DPRINTF(LLSC,"%s: clearing lock flag in handle locked write\n",
130  xc->getCpuPtr()->name());
131  // the rest of this code is not architectural;
132  // it's just a debugging aid to help detect
133  // livelock by warning on long sequences of failed
134  // store conditionals
135  int stCondFailures = xc->readStCondFailures();
136  stCondFailures++;
137  xc->setStCondFailures(stCondFailures);
138  if (stCondFailures % 100000 == 0) {
139  warn("context %d: %d consecutive "
140  "store conditional failures\n",
141  xc->contextId(), stCondFailures);
142  }
143 
144  // store conditional failed already, so don't issue it to mem
145  return false;
146  }
147  return true;
148 }
149 
150 template <class XC>
151 inline void
153 {
154  // A spinlock would typically include a Wait For Event (WFE) to
155  // conserve energy. The ARMv8 architecture specifies that an event
156  // is automatically generated when clearing the exclusive monitor
157  // to wake up the processor in WFE.
158  DPRINTF(LLSC,"Clearing lock and signaling sev\n");
159  xc->setMiscReg(MISCREG_LOCKFLAG, false);
160  // Implement ARMv8 WFE/SEV semantics
161  sendEvent(xc);
162  xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
163 }
164 
165 } // namespace ArmISA
166 } // namespace gem5
167 
168 #endif
warn
#define warn(...)
Definition: logging.hh:245
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:583
gem5::ArmISA::MISCREG_LOCKFLAG
@ MISCREG_LOCKFLAG
Definition: misc.hh:83
request.hh
packet.hh
gem5::ArmISA::handleLockedWrite
bool handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
Definition: locked_mem.hh:113
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::ArmISA::handleLockedSnoopHit
void handleLockedSnoopHit(XC *xc)
Definition: locked_mem.hh:103
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::MISCREG_LOCKADDR
@ MISCREG_LOCKADDR
Definition: misc.hh:82
utility.hh
gem5::ArmISA::globalClearExclusive
void globalClearExclusive(XC *xc)
Definition: locked_mem.hh:152
misc.hh
gem5::ArmISA::sendEvent
void sendEvent(ThreadContext *tc)
Send an event (SEV) to a specific PE if there isn't already a pending event.
Definition: utility.cc:63
gem5::ArmISA::handleLockedRead
void handleLockedRead(XC *xc, const RequestPtr &req)
Definition: locked_mem.hh:93
gem5::ArmISA::MISCREG_SEV_MAILBOX
@ MISCREG_SEV_MAILBOX
Definition: misc.hh:92
gem5::ArmISA::handleLockedSnoop
void handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
Definition: locked_mem.hh:64
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Packet::isInvalidate
bool isInvalidate() const
Definition: packet.hh:598

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