gem5 v24.0.0.0
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display.h
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1/*****************************************************************************
2
3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4 more contributor license agreements. See the NOTICE file distributed
5 with this work for additional information regarding copyright ownership.
6 Accellera licenses this file to you under the Apache License, Version 2.0
7 (the "License"); you may not use this file except in compliance with the
8 License. You may obtain a copy of the License at
9
10 http://www.apache.org/licenses/LICENSE-2.0
11
12 Unless required by applicable law or agreed to in writing, software
13 distributed under the License is distributed on an "AS IS" BASIS,
14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22 display.h --
23
24 Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31 changes you are making here.
32
33 Name, Affiliation, Date:
34 Description of Modification:
35
36 *****************************************************************************/
37
38#include "common.h"
39
40SC_MODULE( display )
41{
42 SC_HAS_PROCESS( display );
43
44 sc_in_clk clk;
45
46 const sc_signal_bool_vector4& in_data1; // Input port
47 const sc_signal_bool_vector5& in_data2; // Input port
48 const sc_signal_bool_vector6& in_data3; // Input port
49 const sc_signal_bool_vector7& in_data4; // Input port
50 const sc_signal_bool_vector8& in_data5; // Input port
51 const sc_signal<bool>& in_valid;
52
53 display( sc_module_name NAME,
54 sc_clock& CLK,
55 const sc_signal_bool_vector4& IN_DATA1,
56 const sc_signal_bool_vector5& IN_DATA2,
57 const sc_signal_bool_vector6& IN_DATA3,
58 const sc_signal_bool_vector7& IN_DATA4,
59 const sc_signal_bool_vector8& IN_DATA5,
60 const sc_signal<bool>& IN_VALID
61 )
62 :
63 in_data1(IN_DATA1),
64 in_data2(IN_DATA2),
65 in_data3(IN_DATA3),
66 in_data4(IN_DATA4),
67 in_data5(IN_DATA5),
68 in_valid(IN_VALID)
69 {
70 clk(CLK);
71 SC_CTHREAD( entry, clk.pos() );
72 }
73
74 void entry();
75};
76
77// EOF
sc_signal< sc_bv< 4 > > sc_signal_bool_vector4
Definition common.h:43
sc_signal< sc_bv< 8 > > sc_signal_bool_vector8
Definition common.h:44
sc_signal< sc_bv< 6 > > sc_signal_bool_vector6
Definition common.h:44
sc_signal< sc_bv< 7 > > sc_signal_bool_vector7
Definition common.h:46
sc_signal< sc_bv< 5 > > sc_signal_bool_vector5
Definition common.h:44
#define SC_CTHREAD(name, clk)
Definition sc_module.hh:323
#define SC_MODULE(name)
Definition sc_module.hh:295
#define SC_HAS_PROCESS(name)
Definition sc_module.hh:301

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