gem5 v24.0.0.0
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mean.h
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1/*****************************************************************************
2
3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4 more contributor license agreements. See the NOTICE file distributed
5 with this work for additional information regarding copyright ownership.
6 Accellera licenses this file to you under the Apache License, Version 2.0
7 (the "License"); you may not use this file except in compliance with the
8 License. You may obtain a copy of the License at
9
10 http://www.apache.org/licenses/LICENSE-2.0
11
12 Unless required by applicable law or agreed to in writing, software
13 distributed under the License is distributed on an "AS IS" BASIS,
14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22 mean.h --
23
24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31 changes you are making here.
32
33 Name, Affiliation, Date:
34 Description of Modification:
35
36 *****************************************************************************/
37
38/* Filename mean.h */
39/* This is the interface file for synchronous process `mean' */
40
41#include "systemc.h"
42
43typedef sc_signal<sc_bv<24> > signal_bool_vector;
44
45SC_MODULE( mean )
46{
47 SC_HAS_PROCESS( mean );
48
49 sc_in_clk clk;
50
51 const signal_bool_vector& a; //input
52 const signal_bool_vector& b; //input
53 const signal_bool_vector& c; //input
54 const signal_bool_vector& d; //input
55 signal_bool_vector& am; //output
56 signal_bool_vector& gm; //output
57 signal_bool_vector& hm; //output
58
59 //Constructor
60 mean(sc_module_name NAME,
61 sc_clock& CLK,
62 const signal_bool_vector& A,
63 const signal_bool_vector& B,
64 const signal_bool_vector& C,
65 const signal_bool_vector& D,
69 : a(A), b(B), c(C), d(D), am(AM), gm(GM), hm(HM)
70 {
71 clk(CLK);
72 SC_CTHREAD( entry, clk.pos() );
73 }
74
75 // Process functionality in member function below
76 void entry();
77};
78
79
sc_signal< sc_bv< 24 > > signal_bool_vector
Definition mean.h:43
SwitchingFiber b
SwitchingFiber c
SwitchingFiber a
#define SC_CTHREAD(name, clk)
Definition sc_module.hh:323
#define SC_MODULE(name)
Definition sc_module.hh:295
#define SC_HAS_PROCESS(name)
Definition sc_module.hh:301
sc_signal< bool_vector > signal_bool_vector
Definition common.h:44

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