gem5  v22.0.0.2
ram.h
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21 
22  ram.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
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29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
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33  Name, Affiliation, Date:
34  Description of Modification:
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36  *****************************************************************************/
37 
38 /* Filename ram.h */
39 /* This is the interface file for asynchronous process 'ram' */
40 
41 #include "common.h"
42 
43 SC_MODULE( ram )
44 {
45  SC_HAS_PROCESS( ram );
46 
47  const signal_bool_vector32& datain; //input
48  const sc_signal<bool>& cs; //input
49  const sc_signal<bool>& we; //input
50  const signal_bool_vector10& addr; //input
51  signal_bool_vector32& dataout; //output
52 
53  //Constructor
54  ram(sc_module_name NAME,
55  const signal_bool_vector32& DATAIN,
56  const sc_signal<bool>& CS,
57  const sc_signal<bool>& WE,
58  const signal_bool_vector10& ADDR,
59  signal_bool_vector32& DATAOUT)
60  : datain(DATAIN), cs(CS), we(WE),
61  addr(ADDR), dataout(DATAOUT)
62  {
63  SC_METHOD( entry );
64  sensitive << datain;
65  sensitive << cs;
66  sensitive << we;
67  sensitive << addr;
68  }
69 
70  // Process functionality in member function below
71  void entry();
72 };
73 
74 
signal_bool_vector10
sc_signal< sc_bv< 10 > > signal_bool_vector10
Definition: common.h:43
SC_MODULE
SC_MODULE(ram)
Definition: ram.h:43
SC_METHOD
#define SC_METHOD(name)
Definition: sc_module.hh:303
signal_bool_vector32
sc_signal< sc_bv< 32 > > signal_bool_vector32
Definition: common.h:44
gem5::X86ISA::CS
const uint8_t CS
Definition: decoder_tables.cc:46
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:301
common.h
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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