gem5 v24.0.0.0
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pipeline.h
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1/*****************************************************************************
2
3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4 more contributor license agreements. See the NOTICE file distributed
5 with this work for additional information regarding copyright ownership.
6 Accellera licenses this file to you under the Apache License, Version 2.0
7 (the "License"); you may not use this file except in compliance with the
8 License. You may obtain a copy of the License at
9
10 http://www.apache.org/licenses/LICENSE-2.0
11
12 Unless required by applicable law or agreed to in writing, software
13 distributed under the License is distributed on an "AS IS" BASIS,
14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22 pipeline.h --
23
24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31 changes you are making here.
32
33 Name, Affiliation, Date:
34 Description of Modification:
35
36 *****************************************************************************/
37
38/* Filename pipeline.h */
39/* This is the interface file for module `pipeline' */
40
41#include "systemc.h"
42
43struct pipeline : public sc_module {
44 sc_signal<double> prod;
45 sc_signal<double> quot;
46
47 stage1_2 S1_2; // component
48 stage3 S3; //component
49
50 //Constructor
51 pipeline(sc_module_name NAME,
52 sc_clock& CLK,
53 const sc_signal<double>& IN1,
54 const sc_signal<double>& IN2,
55 sc_signal<double>& OUT_)
56 : sc_module(NAME),
57 S1_2("Stage1_2", CLK, IN1, IN2, prod, quot),
58 S3("Stage3", CLK, prod, quot, OUT_)
59 {
60 }
61};
62
63
sc_signal< double > quot
Definition pipeline.h:45
sc_signal< double > prod
Definition pipeline.h:44
stage1_2 S1_2
Definition pipeline.h:47
stage3 S3
Definition pipeline.h:48
pipeline(sc_module_name NAME, sc_clock &CLK, const sc_signal< double > &IN1, const sc_signal< double > &IN2, sc_signal< double > &OUT_)
Definition pipeline.h:51

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