gem5  v21.1.0.2
cycle_model.h
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20 /*****************************************************************************
21 
22  cycle_model.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 #include "common.h"
39 
40 #define MEM_SIZE 65536
41 #define INT_SIZE 2048
42 
43 /* types of operands */
44 enum op_type {
46  o_acc, // accumulator
47  o_reg, // registers Ri
48  o_dir, // internal register direct
49  o_ind, // internal register pointed to by R0 or R1
50  o_ext, // external memory pointed to by R0 or R1
51  o_rel, // 2complement offset byte
52  o_cst, // 8bit constant
53  o_lcst, // 16bit constant
54  o_add, // 11bit destination address
55  o_ladd // 16bit destination address
56 };
57 
58 
59 /* limited set of instruction types */
60 enum instr_type {
61  // arithmetic operations
62  i_add, // 0
63  i_sub, // 1
64  i_inc, // 2
65  i_dec, // 3
66  i_mul, // 4
67  i_div, // 5
68  // logic operations
69  i_and, // 6
70  i_or, // 7
71  i_xor, // 8
72  i_clr, // 9
73  i_cpl, // 10
74  i_rl, // 11
75  i_rr, // 12
76  // data transfer
77  i_mov, // 13
78  // branching
79  i_call,// 14
80  i_ret, // 15
81  i_jmp, // 16
82  i_sjmp,// 17
83  i_jz, // 18
84  i_jnz, // 19
85  i_cjne,// 20
86  i_djnz,// 21
87  i_nop // 22
88 };
89 
90 
91 /* cycle types for memory bus */
96 };
97 
98 
99 /* ------------------------------------------------------------------------
100  * struct operand
101  * ----------------------------------------------------------------------*/
102 struct operand {
104  int val; /* value encoded with the opcode (i.e. register number) */
105 };
106 
107 
108 /* ------------------------------------------------------------------------
109  * struct instr ( instruction )
110  * ----------------------------------------------------------------------*/
111 struct instr {
113  int n_src; /* number of source operands */
114  operand src1; /* source operand 1 */
115  operand src2; /* source operand 2 */
116  operand dst; /* destination operand */
117  int cycle; // number of cycles
118 };
119 
120 
121 /* ------------------------------------------------------------------------
122  * struct stack_el ( stack element )
123  * ----------------------------------------------------------------------*/
124 struct stack_el {
125  int address;
127 };
128 
129 
130 
131 /* ------------------------------------------------------------------------
132  * struct cycle_model: public sc_aproc
133  *
134  * ----------------------------------------------------------------------*/
135 
136 SC_MODULE( cycle_model )
137 {
138  SC_HAS_PROCESS( cycle_model );
139 
140  sc_in_clk clk;
141 
142  /* functions */
143  void init();
144  void parse_hex(char *name);
145  void exec_bus_cycle(bus_cycle_type op, int addr, int data, int* result);
146  bool request_address(int addr);
147  int fetch_instr(int ad);
148  int fetch_data(int ad);
149  int write_data(int ad, int data);
150  int fetch_operand(operand* op);
151  int write_back(operand *, int);
152  void execute(instr *i);
153  void decode(int opcode, instr* i);
154 
155 
156  /* memory bus */
157  signal_bool_vector16& mem_addr;
158  signal_bool_vector8& mem_data_out;
159  const signal_bool_vector8& mem_data_in;
160  sc_signal<bool>& mem_wr_n;
161  sc_signal<bool>& mem_rd_n;
162  sc_signal<bool>& mem_pswr_n;
163  sc_signal<bool>& mem_psrd_n;
164  sc_signal<bool>& mem_ale;
165  const sc_signal<bool>& mem_ea_n;
166 
167  sc_signal<bool>& p0_mem_reg_n;
168  sc_signal<bool>& p0_addr_data_n;
169  sc_signal<bool>& p2_mem_reg_n;
170 
171  /* internal variables */
172  /* memories registers and stack */
173  int instr_mem[MEM_SIZE]; /* instruction memory */
174  int ext_mem[MEM_SIZE]; /* 'external' data memory */
175  int int_mem[INT_SIZE]; /* internal data memory */
176  int A; /* accumulator */
177  int R[8]; /* registers */
178  stack_el *my_stack; /* stack */
179  /* others */
180  int cycles2execute; /* number of cycles to execute */
181  int cycle_count; /* total number of cycles executed */
182  int stretch_cycles; /* memory stretch cycles */
183 
184 
185 
186  /* Constructor */
187  cycle_model(sc_module_name NAME,
188  const sc_signal_in_if<bool>& CLK,
189  char* hex_file_name,
190 
191  signal_bool_vector16& MEM_ADDR,
192  signal_bool_vector8& MEM_DATA_OUT,
193  const signal_bool_vector8& MEM_DATA_IN,
194  sc_signal<bool>& MEM_WR_N,
195  sc_signal<bool>& MEM_RD_N,
196  sc_signal<bool>& MEM_PSWR_N,
197  sc_signal<bool>& MEM_PSRD_N,
198  sc_signal<bool>& MEM_ALE,
199  const sc_signal<bool>& MEM_EA_N,
200 
201  sc_signal<bool>& P0_MEM_REG_N,
202  sc_signal<bool>& P0_ADDR_DATA_N,
203  sc_signal<bool>& P2_MEM_REG_N
204  )
205  :
206 
207  mem_addr(MEM_ADDR),
208  mem_data_out(MEM_DATA_OUT),
209  mem_data_in(MEM_DATA_IN),
210  mem_wr_n(MEM_WR_N),
211  mem_rd_n(MEM_RD_N),
212  mem_pswr_n(MEM_PSWR_N),
213  mem_psrd_n(MEM_PSRD_N),
214  mem_ale(MEM_ALE),
215  mem_ea_n(MEM_EA_N),
216  p0_mem_reg_n(P0_MEM_REG_N),
217  p0_addr_data_n(P0_ADDR_DATA_N),
218  p2_mem_reg_n(P2_MEM_REG_N)
219  {
220  clk(CLK);
221  SC_THREAD( entry );
222  sensitive << clk;
223 
224  parse_hex(hex_file_name);
225  init();
226  }
227 
228  /* Process functionality in member function below */
229  void entry();
230 };
i_sub
@ i_sub
Definition: cycle_model.h:63
instr
Definition: cycle_model.h:111
SC_THREAD
#define SC_THREAD(name)
Definition: sc_module.hh:310
instr_type
instr_type
Definition: cycle_model.h:60
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::X86ISA::R
R
Definition: int.hh:51
common.h
i_mul
@ i_mul
Definition: cycle_model.h:66
stack_el::address
int address
Definition: cycle_model.h:125
o_cst
@ o_cst
Definition: cycle_model.h:52
o_rel
@ o_rel
Definition: cycle_model.h:51
SC_MODULE
SC_MODULE(cycle_model)
Definition: cycle_model.h:136
o_ladd
@ o_ladd
Definition: cycle_model.h:55
instr::src2
operand src2
Definition: cycle_model.h:115
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
i_mov
@ i_mov
Definition: cycle_model.h:77
operand
Definition: cycle_model.h:102
INT_SIZE
#define INT_SIZE
Definition: cycle_model.h:41
instr::cycle
int cycle
Definition: cycle_model.h:117
i_dec
@ i_dec
Definition: cycle_model.h:65
bus_cycle_type
bus_cycle_type
Definition: cycle_model.h:92
i_sjmp
@ i_sjmp
Definition: cycle_model.h:82
instr::type
instr_type type
Definition: cycle_model.h:112
instr::n_src
int n_src
Definition: cycle_model.h:113
o_add
@ o_add
Definition: cycle_model.h:54
op_type
op_type
Definition: cycle_model.h:44
i_div
@ i_div
Definition: cycle_model.h:67
gem5::ArmISA::opcode
Bitfield< 24, 21 > opcode
Definition: types.hh:92
stack_el::up
stack_el * up
Definition: cycle_model.h:126
instr::dst
operand dst
Definition: cycle_model.h:116
i_djnz
@ i_djnz
Definition: cycle_model.h:86
instr::src1
operand src1
Definition: cycle_model.h:114
i_cjne
@ i_cjne
Definition: cycle_model.h:85
o_acc
@ o_acc
Definition: cycle_model.h:46
i_and
@ i_and
Definition: cycle_model.h:69
i_nop
@ i_nop
Definition: cycle_model.h:87
i_clr
@ i_clr
Definition: cycle_model.h:72
i_or
@ i_or
Definition: cycle_model.h:70
i_xor
@ i_xor
Definition: cycle_model.h:71
o_null
@ o_null
Definition: cycle_model.h:45
i_inc
@ i_inc
Definition: cycle_model.h:64
o_lcst
@ o_lcst
Definition: cycle_model.h:53
i_call
@ i_call
Definition: cycle_model.h:79
operand::type
op_type type
Definition: cycle_model.h:103
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
i_jnz
@ i_jnz
Definition: cycle_model.h:84
o_ext
@ o_ext
Definition: cycle_model.h:50
name
const std::string & name()
Definition: trace.cc:49
MEM_SIZE
#define MEM_SIZE
Definition: cycle_model.h:40
OP_IDLE
@ OP_IDLE
Definition: cycle_model.h:93
i_rl
@ i_rl
Definition: cycle_model.h:74
i_add
@ i_add
Definition: cycle_model.h:62
i_ret
@ i_ret
Definition: cycle_model.h:80
OP_MEM_READ
@ OP_MEM_READ
Definition: cycle_model.h:94
operand::val
int val
Definition: cycle_model.h:104
OP_MEM_WRITE
@ OP_MEM_WRITE
Definition: cycle_model.h:95
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:298
stack_el
Definition: cycle_model.h:124
o_ind
@ o_ind
Definition: cycle_model.h:49
gem5::statistics::init
const FlagsType init
This Stat is Initialized.
Definition: info.hh:56
i_jz
@ i_jz
Definition: cycle_model.h:83
i_cpl
@ i_cpl
Definition: cycle_model.h:73
i_jmp
@ i_jmp
Definition: cycle_model.h:81
o_reg
@ o_reg
Definition: cycle_model.h:47
i_rr
@ i_rr
Definition: cycle_model.h:75
signal_bool_vector8
sc_signal< sc_bv< 8 > > signal_bool_vector8
Definition: common.h:43
o_dir
@ o_dir
Definition: cycle_model.h:48
gem5::X86ISA::op
Bitfield< 4 > op
Definition: types.hh:83
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
signal_bool_vector16
sc_signal< sc_bv< 16 > > signal_bool_vector16
Definition: common.h:44

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