gem5  v21.1.0.2
gpu_isa.hh
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33 
34 #ifndef __ARCH_GCN3_GPU_ISA_HH__
35 #define __ARCH_GCN3_GPU_ISA_HH__
36 
37 #include <array>
38 #include <type_traits>
39 
43 #include "gpu-compute/misc.hh"
44 
45 namespace gem5
46 {
47 
48 class Wavefront;
49 
50 namespace Gcn3ISA
51 {
52  class GPUISA
53  {
54  public:
55  GPUISA(Wavefront &wf);
56 
57  template<typename T> T
58  readConstVal(int opIdx) const
59  {
60  panic_if(!std::is_integral<T>::value, "Constant values must "
61  "be an integer.\n");
62  T val(0);
63 
64  if (isPosConstVal(opIdx)) {
65  val = (T)readPosConstReg(opIdx);
66  }
67 
68  if (isNegConstVal(opIdx)) {
69  val = (T)readNegConstReg(opIdx);
70  }
71 
72  return val;
73  }
74 
75  ScalarRegU32 readMiscReg(int opIdx) const;
76  void writeMiscReg(int opIdx, ScalarRegU32 operandVal);
77  bool hasScalarUnit() const { return true; }
78  void advancePC(GPUDynInstPtr gpuDynInst);
79 
80  private:
81  ScalarRegU32 readPosConstReg(int opIdx) const
82  {
83  return posConstRegs[opIdx - REG_INT_CONST_POS_MIN];
84  }
85 
86  ScalarRegI32 readNegConstReg(int opIdx) const
87  {
88  return negConstRegs[opIdx - REG_INT_CONST_NEG_MIN];
89  }
90 
91  static const std::array<const ScalarRegU32, NumPosConstRegs>
93  static const std::array<const ScalarRegI32, NumNegConstRegs>
95 
96  // parent wavefront
98 
99  // shader status bits
101  // memory descriptor reg
103  };
104 } // namespace Gcn3ISA
105 } // namespace gem5
106 
107 #endif // __ARCH_GCN3_GPU_ISA_HH__
gem5::Gcn3ISA::GPUISA::statusReg
StatusReg statusReg
Definition: gpu_isa.hh:100
hsa_queue_entry.hh
gem5::Gcn3ISA::GPUISA::writeMiscReg
void writeMiscReg(int opIdx, ScalarRegU32 operandVal)
Definition: isa.cc:68
gem5::Gcn3ISA::GPUISA::wavefront
Wavefront & wavefront
Definition: gpu_isa.hh:97
gem5::Gcn3ISA::isNegConstVal
bool isNegConstVal(int opIdx)
Definition: registers.cc:178
gem5::Gcn3ISA::GPUISA::advancePC
void advancePC(GPUDynInstPtr gpuDynInst)
Definition: isa.cc:85
gem5::Gcn3ISA::isPosConstVal
bool isPosConstVal(int opIdx)
Definition: registers.cc:169
gem5::Wavefront
Definition: wavefront.hh:62
gpu_registers.hh
gem5::Gcn3ISA::GPUISA::m0
ScalarRegU32 m0
Definition: gpu_isa.hh:102
misc.hh
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::Gcn3ISA::GPUISA::negConstRegs
static const std::array< const ScalarRegI32, NumNegConstRegs > negConstRegs
Definition: gpu_isa.hh:94
gem5::Gcn3ISA::ScalarRegI32
int32_t ScalarRegI32
Definition: gpu_registers.hh:156
gem5::Gcn3ISA::GPUISA
Definition: gpu_isa.hh:52
gem5::Gcn3ISA::GPUISA::readMiscReg
ScalarRegU32 readMiscReg(int opIdx) const
Definition: isa.cc:51
gem5::Gcn3ISA::GPUISA::readPosConstReg
ScalarRegU32 readPosConstReg(int opIdx) const
Definition: gpu_isa.hh:81
gem5::Gcn3ISA::GPUISA::GPUISA
GPUISA(Wavefront &wf)
Definition: isa.cc:46
gem5::Gcn3ISA::GPUISA::hasScalarUnit
bool hasScalarUnit() const
Definition: gpu_isa.hh:77
gem5::Gcn3ISA::GPUISA::readNegConstReg
ScalarRegI32 readNegConstReg(int opIdx) const
Definition: gpu_isa.hh:86
gem5::Gcn3ISA::REG_INT_CONST_POS_MIN
@ REG_INT_CONST_POS_MIN
Definition: gpu_registers.hh:81
gem5::Gcn3ISA::GPUISA::posConstRegs
static const std::array< const ScalarRegU32, NumPosConstRegs > posConstRegs
Definition: gpu_isa.hh:92
gem5::Gcn3ISA::StatusReg
Definition: gpu_registers.hh:183
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:51
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::Gcn3ISA::GPUISA::readConstVal
T readConstVal(int opIdx) const
Definition: gpu_isa.hh:58
dispatcher.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Gcn3ISA::ScalarRegU32
uint32_t ScalarRegU32
Definition: gpu_registers.hh:155
gem5::Gcn3ISA::REG_INT_CONST_NEG_MIN
@ REG_INT_CONST_NEG_MIN
Definition: gpu_registers.hh:83

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