gem5  v22.0.0.2
Classes | Namespaces | Typedefs | Enumerations | Functions | Variables
gpu_registers.hh File Reference
#include <array>
#include <cstdint>
#include <string>
#include "arch/generic/vec_reg.hh"
#include "base/intmath.hh"
#include "base/logging.hh"

Go to the source code of this file.

Classes

struct  gem5::Gcn3ISA::StatusReg
 

Namespaces

 gem5
 Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
 
 gem5::Gcn3ISA
 classes that represnt vector/scalar operands in GCN3 ISA.
 

Typedefs

typedef uint8_t gem5::Gcn3ISA::ScalarRegU8
 
typedef int8_t gem5::Gcn3ISA::ScalarRegI8
 
typedef uint16_t gem5::Gcn3ISA::ScalarRegU16
 
typedef int16_t gem5::Gcn3ISA::ScalarRegI16
 
typedef uint32_t gem5::Gcn3ISA::ScalarRegU32
 
typedef int32_t gem5::Gcn3ISA::ScalarRegI32
 
typedef float gem5::Gcn3ISA::ScalarRegF32
 
typedef uint64_t gem5::Gcn3ISA::ScalarRegU64
 
typedef int64_t gem5::Gcn3ISA::ScalarRegI64
 
typedef double gem5::Gcn3ISA::ScalarRegF64
 
typedef uint8_t gem5::Gcn3ISA::VecElemU8
 
typedef int8_t gem5::Gcn3ISA::VecElemI8
 
typedef uint16_t gem5::Gcn3ISA::VecElemU16
 
typedef int16_t gem5::Gcn3ISA::VecElemI16
 
typedef uint32_t gem5::Gcn3ISA::VecElemU32
 
typedef int32_t gem5::Gcn3ISA::VecElemI32
 
typedef float gem5::Gcn3ISA::VecElemF32
 
typedef uint64_t gem5::Gcn3ISA::VecElemU64
 
typedef int64_t gem5::Gcn3ISA::VecElemI64
 
typedef double gem5::Gcn3ISA::VecElemF64
 
using gem5::Gcn3ISA::VecRegContainerU32 = VecRegContainer< sizeof(VecElemU32) *NumVecElemPerVecReg >
 

Enumerations

enum  gem5::Gcn3ISA::OpSelector : int {
  gem5::Gcn3ISA::REG_SGPR_MIN = 0, gem5::Gcn3ISA::REG_SGPR_MAX = 101, gem5::Gcn3ISA::REG_FLAT_SCRATCH_LO = 102, gem5::Gcn3ISA::REG_FLAT_SCRATCH_HI = 103,
  gem5::Gcn3ISA::REG_XNACK_MASK_LO = 104, gem5::Gcn3ISA::REG_XNACK_MASK_HI = 105, gem5::Gcn3ISA::REG_VCC_LO = 106, gem5::Gcn3ISA::REG_VCC_HI = 107,
  gem5::Gcn3ISA::REG_TBA_LO = 108, gem5::Gcn3ISA::REG_TBA_HI = 109, gem5::Gcn3ISA::REG_TMA_LO = 110, gem5::Gcn3ISA::REG_TMA_HI = 111,
  gem5::Gcn3ISA::REG_TTMP_0 = 112, gem5::Gcn3ISA::REG_TTMP_1 = 113, gem5::Gcn3ISA::REG_TTMP_2 = 114, gem5::Gcn3ISA::REG_TTMP_3 = 115,
  gem5::Gcn3ISA::REG_TTMP_4 = 116, gem5::Gcn3ISA::REG_TTMP_5 = 117, gem5::Gcn3ISA::REG_TTMP_6 = 118, gem5::Gcn3ISA::REG_TTMP_7 = 119,
  gem5::Gcn3ISA::REG_TTMP_8 = 120, gem5::Gcn3ISA::REG_TTMP_9 = 121, gem5::Gcn3ISA::REG_TTMP_10 = 122, gem5::Gcn3ISA::REG_TTMP_11 = 123,
  gem5::Gcn3ISA::REG_M0 = 124, gem5::Gcn3ISA::REG_RESERVED_1 = 125, gem5::Gcn3ISA::REG_EXEC_LO = 126, gem5::Gcn3ISA::REG_EXEC_HI = 127,
  gem5::Gcn3ISA::REG_ZERO = 128, gem5::Gcn3ISA::REG_INT_CONST_POS_MIN = 129, gem5::Gcn3ISA::REG_INT_CONST_POS_MAX = 192, gem5::Gcn3ISA::REG_INT_CONST_NEG_MIN = 193,
  gem5::Gcn3ISA::REG_INT_CONST_NEG_MAX = 208, gem5::Gcn3ISA::REG_RESERVED_2 = 209, gem5::Gcn3ISA::REG_RESERVED_3 = 210, gem5::Gcn3ISA::REG_RESERVED_4 = 211,
  gem5::Gcn3ISA::REG_RESERVED_5 = 212, gem5::Gcn3ISA::REG_RESERVED_6 = 213, gem5::Gcn3ISA::REG_RESERVED_7 = 214, gem5::Gcn3ISA::REG_RESERVED_8 = 215,
  gem5::Gcn3ISA::REG_RESERVED_9 = 216, gem5::Gcn3ISA::REG_RESERVED_10 = 217, gem5::Gcn3ISA::REG_RESERVED_11 = 218, gem5::Gcn3ISA::REG_RESERVED_12 = 219,
  gem5::Gcn3ISA::REG_RESERVED_13 = 220, gem5::Gcn3ISA::REG_RESERVED_14 = 221, gem5::Gcn3ISA::REG_RESERVED_15 = 222, gem5::Gcn3ISA::REG_RESERVED_16 = 223,
  gem5::Gcn3ISA::REG_RESERVED_17 = 224, gem5::Gcn3ISA::REG_RESERVED_18 = 225, gem5::Gcn3ISA::REG_RESERVED_19 = 226, gem5::Gcn3ISA::REG_RESERVED_20 = 227,
  gem5::Gcn3ISA::REG_RESERVED_21 = 228, gem5::Gcn3ISA::REG_RESERVED_22 = 229, gem5::Gcn3ISA::REG_RESERVED_23 = 230, gem5::Gcn3ISA::REG_RESERVED_24 = 231,
  gem5::Gcn3ISA::REG_RESERVED_25 = 232, gem5::Gcn3ISA::REG_RESERVED_26 = 233, gem5::Gcn3ISA::REG_RESERVED_27 = 234, gem5::Gcn3ISA::REG_RESERVED_28 = 235,
  gem5::Gcn3ISA::REG_RESERVED_29 = 236, gem5::Gcn3ISA::REG_RESERVED_30 = 237, gem5::Gcn3ISA::REG_RESERVED_31 = 238, gem5::Gcn3ISA::REG_RESERVED_32 = 239,
  gem5::Gcn3ISA::REG_POS_HALF = 240, gem5::Gcn3ISA::REG_NEG_HALF = 241, gem5::Gcn3ISA::REG_POS_ONE = 242, gem5::Gcn3ISA::REG_NEG_ONE = 243,
  gem5::Gcn3ISA::REG_POS_TWO = 244, gem5::Gcn3ISA::REG_NEG_TWO = 245, gem5::Gcn3ISA::REG_POS_FOUR = 246, gem5::Gcn3ISA::REG_NEG_FOUR = 247,
  gem5::Gcn3ISA::REG_PI = 248, gem5::Gcn3ISA::REG_SRC_SWDA = 249, gem5::Gcn3ISA::REG_SRC_DPP = 250, gem5::Gcn3ISA::REG_VCCZ = 251,
  gem5::Gcn3ISA::REG_EXECZ = 252, gem5::Gcn3ISA::REG_SCC = 253, gem5::Gcn3ISA::REG_LDS_DIRECT = 254, gem5::Gcn3ISA::REG_SRC_LITERAL = 255,
  gem5::Gcn3ISA::REG_VGPR_MIN = 256, gem5::Gcn3ISA::REG_VGPR_MAX = 511
}
 

Functions

constexpr size_t gem5::Gcn3ISA::MaxOperandDwords (16)
 
const int gem5::Gcn3ISA::NumVecElemPerVecReg (64)
 
std::string gem5::Gcn3ISA::opSelectorToRegSym (int opIdx, int numRegs=0)
 
int gem5::Gcn3ISA::opSelectorToRegIdx (int opIdx, int numScalarRegs)
 
bool gem5::Gcn3ISA::isPosConstVal (int opIdx)
 
bool gem5::Gcn3ISA::isNegConstVal (int opIdx)
 
bool gem5::Gcn3ISA::isConstVal (int opIdx)
 
bool gem5::Gcn3ISA::isLiteral (int opIdx)
 
bool gem5::Gcn3ISA::isScalarReg (int opIdx)
 
bool gem5::Gcn3ISA::isVectorReg (int opIdx)
 
bool gem5::Gcn3ISA::isFlatScratchReg (int opIdx)
 
bool gem5::Gcn3ISA::isExecMask (int opIdx)
 
bool gem5::Gcn3ISA::isVccReg (int opIdx)
 

Variables

const int gem5::Gcn3ISA::NumPosConstRegs
 
const int gem5::Gcn3ISA::NumNegConstRegs
 
const int gem5::Gcn3ISA::BITS_PER_BYTE = 8
 
const int gem5::Gcn3ISA::BITS_PER_WORD = 16
 
const int gem5::Gcn3ISA::MSB_PER_BYTE = (BITS_PER_BYTE - 1)
 
const int gem5::Gcn3ISA::MSB_PER_WORD = (BITS_PER_WORD - 1)
 
const int gem5::Gcn3ISA::DWordSize = sizeof(VecElemU32)
 
const int gem5::Gcn3ISA::RegSizeDWords = sizeof(VecElemU32) / DWordSize
 Size of a single-precision register in DWords. More...
 

Generated on Thu Jul 28 2022 13:32:43 for gem5 by doxygen 1.8.17