gem5  v22.0.0.2
gpu_registers.hh
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31 
32 #ifndef __ARCH_GCN3_REGISTERS_HH__
33 #define __ARCH_GCN3_REGISTERS_HH__
34 
35 #include <array>
36 #include <cstdint>
37 #include <string>
38 
39 #include "arch/generic/vec_reg.hh"
40 #include "base/intmath.hh"
41 #include "base/logging.hh"
42 
43 namespace gem5
44 {
45 
46 namespace Gcn3ISA
47 {
48  enum OpSelector : int
49  {
51  REG_SGPR_MAX = 101,
56  REG_VCC_LO = 106,
57  REG_VCC_HI = 107,
58  REG_TBA_LO = 108,
59  REG_TBA_HI = 109,
60  REG_TMA_LO = 110,
61  REG_TMA_HI = 111,
62  REG_TTMP_0 = 112,
63  REG_TTMP_1 = 113,
64  REG_TTMP_2 = 114,
65  REG_TTMP_3 = 115,
66  REG_TTMP_4 = 116,
67  REG_TTMP_5 = 117,
68  REG_TTMP_6 = 118,
69  REG_TTMP_7 = 119,
70  REG_TTMP_8 = 120,
71  REG_TTMP_9 = 121,
72  REG_TTMP_10 = 122,
73  REG_TTMP_11 = 123,
74  REG_M0 = 124,
76  REG_EXEC_LO = 126,
77  REG_EXEC_HI = 127,
78  REG_ZERO = 128,
116  REG_POS_ONE = 242,
117  REG_NEG_ONE = 243,
118  REG_POS_TWO = 244,
119  REG_NEG_TWO = 245,
122  REG_PI = 248,
123  /* NOTE: SDWA and SWDA both refer to sub d-word addressing */
125  REG_SRC_DPP = 250,
126  REG_VCCZ = 251,
127  REG_EXECZ = 252,
128  REG_SCC = 253,
133  };
134 
135  constexpr size_t MaxOperandDwords(16);
136  const int NumVecElemPerVecReg(64);
137  // op selector values 129 - 192 correspond to const values 1 - 64
139  - REG_INT_CONST_POS_MIN + 1;
140  // op selector values 193 - 208 correspond to const values -1 - 16
142  - REG_INT_CONST_NEG_MIN + 1;
143  const int BITS_PER_BYTE = 8;
144  const int BITS_PER_WORD = 16;
145  const int MSB_PER_BYTE = (BITS_PER_BYTE - 1);
146  const int MSB_PER_WORD = (BITS_PER_WORD - 1);
147 
148  // typedefs for the various sizes/types of scalar regs
149  typedef uint8_t ScalarRegU8;
150  typedef int8_t ScalarRegI8;
151  typedef uint16_t ScalarRegU16;
152  typedef int16_t ScalarRegI16;
153  typedef uint32_t ScalarRegU32;
154  typedef int32_t ScalarRegI32;
155  typedef float ScalarRegF32;
156  typedef uint64_t ScalarRegU64;
157  typedef int64_t ScalarRegI64;
158  typedef double ScalarRegF64;
159 
160  // typedefs for the various sizes/types of vector reg elements
161  typedef uint8_t VecElemU8;
162  typedef int8_t VecElemI8;
163  typedef uint16_t VecElemU16;
164  typedef int16_t VecElemI16;
165  typedef uint32_t VecElemU32;
166  typedef int32_t VecElemI32;
167  typedef float VecElemF32;
168  typedef uint64_t VecElemU64;
169  typedef int64_t VecElemI64;
170  typedef double VecElemF64;
171 
172  const int DWordSize = sizeof(VecElemU32);
176  const int RegSizeDWords = sizeof(VecElemU32) / DWordSize;
177 
178  using VecRegContainerU32 =
180 
181  struct StatusReg
182  {
183  StatusReg() : SCC(0), SPI_PRIO(0), USER_PRIO(0), PRIV(0), TRAP_EN(0),
184  TTRACE_EN(0), EXPORT_RDY(0), EXECZ(0), VCCZ(0), IN_TG(0),
185  IN_BARRIER(0), HALT(0), TRAP(0), TTRACE_CU_EN(0), VALID(0),
186  ECC_ERR(0), SKIP_EXPORT(0), PERF_EN(0), COND_DBG_USER(0),
188  MUST_EXPORT(0), RESERVED_1(0)
189  {
190  }
191 
192  uint32_t SCC : 1;
193  uint32_t SPI_PRIO : 2;
194  uint32_t USER_PRIO : 2;
195  uint32_t PRIV : 1;
196  uint32_t TRAP_EN : 1;
197  uint32_t TTRACE_EN : 1;
198  uint32_t EXPORT_RDY : 1;
199  uint32_t EXECZ : 1;
200  uint32_t VCCZ : 1;
201  uint32_t IN_TG : 1;
202  uint32_t IN_BARRIER : 1;
203  uint32_t HALT : 1;
204  uint32_t TRAP : 1;
205  uint32_t TTRACE_CU_EN : 1;
206  uint32_t VALID : 1;
207  uint32_t ECC_ERR : 1;
208  uint32_t SKIP_EXPORT : 1;
209  uint32_t PERF_EN : 1;
210  uint32_t COND_DBG_USER : 1;
211  uint32_t COND_DBG_SYS : 1;
212  uint32_t ALLOW_REPLAY : 1;
213  uint32_t INSTRUCTION_ATC : 1;
214  uint32_t RESERVED : 3;
215  uint32_t MUST_EXPORT : 1;
216  uint32_t RESERVED_1 : 4;
217  };
218 
219  std::string opSelectorToRegSym(int opIdx, int numRegs=0);
220  int opSelectorToRegIdx(int opIdx, int numScalarRegs);
221  bool isPosConstVal(int opIdx);
222  bool isNegConstVal(int opIdx);
223  bool isConstVal(int opIdx);
224  bool isLiteral(int opIdx);
225  bool isScalarReg(int opIdx);
226  bool isVectorReg(int opIdx);
227  bool isFlatScratchReg(int opIdx);
228  bool isExecMask(int opIdx);
229  bool isVccReg(int opIdx);
230 } // namespace Gcn3ISA
231 } // namespace gem5
232 
233 #endif // __ARCH_GCN3_REGISTERS_HH__
gem5::Gcn3ISA::REG_RESERVED_16
@ REG_RESERVED_16
Definition: gpu_registers.hh:97
gem5::Gcn3ISA::REG_TTMP_11
@ REG_TTMP_11
Definition: gpu_registers.hh:73
gem5::Gcn3ISA::StatusReg::TRAP_EN
uint32_t TRAP_EN
Definition: gpu_registers.hh:196
gem5::Gcn3ISA::REG_VGPR_MIN
@ REG_VGPR_MIN
Definition: gpu_registers.hh:131
gem5::Gcn3ISA::StatusReg::EXECZ
uint32_t EXECZ
Definition: gpu_registers.hh:199
gem5::Gcn3ISA::REG_NEG_TWO
@ REG_NEG_TWO
Definition: gpu_registers.hh:119
gem5::Gcn3ISA::REG_RESERVED_8
@ REG_RESERVED_8
Definition: gpu_registers.hh:89
gem5::Gcn3ISA::REG_SRC_DPP
@ REG_SRC_DPP
Definition: gpu_registers.hh:125
gem5::Gcn3ISA::REG_TTMP_10
@ REG_TTMP_10
Definition: gpu_registers.hh:72
gem5::Gcn3ISA::REG_TBA_HI
@ REG_TBA_HI
Definition: gpu_registers.hh:59
gem5::Gcn3ISA::REG_EXEC_LO
@ REG_EXEC_LO
Definition: gpu_registers.hh:76
gem5::Gcn3ISA::VecElemI32
int32_t VecElemI32
Definition: gpu_registers.hh:166
gem5::Gcn3ISA::REG_INT_CONST_POS_MIN
@ REG_INT_CONST_POS_MIN
Definition: gpu_registers.hh:79
gem5::Gcn3ISA::isNegConstVal
bool isNegConstVal(int opIdx)
Definition: registers.cc:176
gem5::Gcn3ISA::REG_RESERVED_13
@ REG_RESERVED_13
Definition: gpu_registers.hh:94
gem5::Gcn3ISA::isScalarReg
bool isScalarReg(int opIdx)
Definition: registers.cc:216
gem5::Gcn3ISA::REG_RESERVED_28
@ REG_RESERVED_28
Definition: gpu_registers.hh:109
gem5::Gcn3ISA::REG_SGPR_MIN
@ REG_SGPR_MIN
Definition: gpu_registers.hh:50
gem5::Gcn3ISA::REG_RESERVED_11
@ REG_RESERVED_11
Definition: gpu_registers.hh:92
gem5::Gcn3ISA::StatusReg::RESERVED
uint32_t RESERVED
Definition: gpu_registers.hh:214
gem5::Gcn3ISA::ScalarRegF32
float ScalarRegF32
Definition: gpu_registers.hh:155
gem5::Gcn3ISA::StatusReg::COND_DBG_USER
uint32_t COND_DBG_USER
Definition: gpu_registers.hh:210
gem5::Gcn3ISA::REG_RESERVED_5
@ REG_RESERVED_5
Definition: gpu_registers.hh:86
gem5::Gcn3ISA::REG_XNACK_MASK_HI
@ REG_XNACK_MASK_HI
Definition: gpu_registers.hh:55
gem5::Gcn3ISA::isPosConstVal
bool isPosConstVal(int opIdx)
Definition: registers.cc:167
gem5::Gcn3ISA::StatusReg::IN_BARRIER
uint32_t IN_BARRIER
Definition: gpu_registers.hh:202
gem5::Gcn3ISA::opSelectorToRegSym
std::string opSelectorToRegSym(int opIdx, int numRegs=0)
Definition: registers.cc:40
gem5::Gcn3ISA::REG_RESERVED_27
@ REG_RESERVED_27
Definition: gpu_registers.hh:108
gem5::Gcn3ISA::VecElemU32
uint32_t VecElemU32
Definition: gpu_registers.hh:165
gem5::Gcn3ISA::REG_TTMP_4
@ REG_TTMP_4
Definition: gpu_registers.hh:66
gem5::Gcn3ISA::REG_RESERVED_7
@ REG_RESERVED_7
Definition: gpu_registers.hh:88
gem5::Gcn3ISA::REG_RESERVED_14
@ REG_RESERVED_14
Definition: gpu_registers.hh:95
gem5::Gcn3ISA::REG_POS_TWO
@ REG_POS_TWO
Definition: gpu_registers.hh:118
gem5::Gcn3ISA::StatusReg::PRIV
uint32_t PRIV
Definition: gpu_registers.hh:195
gem5::Gcn3ISA::REG_RESERVED_19
@ REG_RESERVED_19
Definition: gpu_registers.hh:100
gem5::Gcn3ISA::MSB_PER_WORD
const int MSB_PER_WORD
Definition: gpu_registers.hh:146
gem5::Gcn3ISA::REG_RESERVED_31
@ REG_RESERVED_31
Definition: gpu_registers.hh:112
gem5::Gcn3ISA::REG_EXEC_HI
@ REG_EXEC_HI
Definition: gpu_registers.hh:77
gem5::Gcn3ISA::REG_TMA_LO
@ REG_TMA_LO
Definition: gpu_registers.hh:60
gem5::Gcn3ISA::REG_RESERVED_3
@ REG_RESERVED_3
Definition: gpu_registers.hh:84
gem5::Gcn3ISA::REG_SRC_LITERAL
@ REG_SRC_LITERAL
Definition: gpu_registers.hh:130
gem5::Gcn3ISA::REG_NEG_FOUR
@ REG_NEG_FOUR
Definition: gpu_registers.hh:121
gem5::Gcn3ISA::REG_RESERVED_25
@ REG_RESERVED_25
Definition: gpu_registers.hh:106
gem5::Gcn3ISA::ScalarRegI32
int32_t ScalarRegI32
Definition: gpu_registers.hh:154
gem5::Gcn3ISA::REG_NEG_ONE
@ REG_NEG_ONE
Definition: gpu_registers.hh:117
gem5::Gcn3ISA::ScalarRegU16
uint16_t ScalarRegU16
Definition: gpu_registers.hh:151
gem5::Gcn3ISA::StatusReg::USER_PRIO
uint32_t USER_PRIO
Definition: gpu_registers.hh:194
gem5::Gcn3ISA::REG_VCCZ
@ REG_VCCZ
Definition: gpu_registers.hh:126
gem5::Gcn3ISA::isVccReg
bool isVccReg(int opIdx)
Definition: registers.cc:204
gem5::Gcn3ISA::StatusReg::IN_TG
uint32_t IN_TG
Definition: gpu_registers.hh:201
gem5::Gcn3ISA::BITS_PER_WORD
const int BITS_PER_WORD
Definition: gpu_registers.hh:144
gem5::Gcn3ISA::REG_VCC_LO
@ REG_VCC_LO
Definition: gpu_registers.hh:56
gem5::Gcn3ISA::REG_RESERVED_24
@ REG_RESERVED_24
Definition: gpu_registers.hh:105
gem5::Gcn3ISA::StatusReg::ALLOW_REPLAY
uint32_t ALLOW_REPLAY
Definition: gpu_registers.hh:212
gem5::Gcn3ISA::REG_TTMP_3
@ REG_TTMP_3
Definition: gpu_registers.hh:65
gem5::Gcn3ISA::isExecMask
bool isExecMask(int opIdx)
Definition: registers.cc:198
gem5::Gcn3ISA::ScalarRegI16
int16_t ScalarRegI16
Definition: gpu_registers.hh:152
gem5::Gcn3ISA::ScalarRegI64
int64_t ScalarRegI64
Definition: gpu_registers.hh:157
gem5::Gcn3ISA::REG_SCC
@ REG_SCC
Definition: gpu_registers.hh:128
gem5::Gcn3ISA::StatusReg::EXPORT_RDY
uint32_t EXPORT_RDY
Definition: gpu_registers.hh:198
gem5::Gcn3ISA::StatusReg::MUST_EXPORT
uint32_t MUST_EXPORT
Definition: gpu_registers.hh:215
gem5::Gcn3ISA::StatusReg::COND_DBG_SYS
uint32_t COND_DBG_SYS
Definition: gpu_registers.hh:211
gem5::Gcn3ISA::REG_RESERVED_20
@ REG_RESERVED_20
Definition: gpu_registers.hh:101
gem5::Gcn3ISA::REG_TTMP_7
@ REG_TTMP_7
Definition: gpu_registers.hh:69
gem5::Gcn3ISA::REG_INT_CONST_NEG_MIN
@ REG_INT_CONST_NEG_MIN
Definition: gpu_registers.hh:81
gem5::Gcn3ISA::REG_SGPR_MAX
@ REG_SGPR_MAX
Definition: gpu_registers.hh:51
gem5::Gcn3ISA::ScalarRegU8
uint8_t ScalarRegU8
Definition: gpu_registers.hh:149
gem5::Gcn3ISA::REG_RESERVED_22
@ REG_RESERVED_22
Definition: gpu_registers.hh:103
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:123
gem5::Gcn3ISA::StatusReg::StatusReg
StatusReg()
Definition: gpu_registers.hh:183
gem5::Gcn3ISA::VecElemF32
float VecElemF32
Definition: gpu_registers.hh:167
gem5::Gcn3ISA::OpSelector
OpSelector
Definition: gpu_registers.hh:48
gem5::Gcn3ISA::NumNegConstRegs
const int NumNegConstRegs
Definition: gpu_registers.hh:141
gem5::Gcn3ISA::isVectorReg
bool isVectorReg(int opIdx)
Definition: registers.cc:229
gem5::Gcn3ISA::isLiteral
bool isLiteral(int opIdx)
Definition: registers.cc:192
gem5::Gcn3ISA::REG_FLAT_SCRATCH_LO
@ REG_FLAT_SCRATCH_LO
Definition: gpu_registers.hh:52
gem5::Gcn3ISA::opSelectorToRegIdx
int opSelectorToRegIdx(int opIdx, int numScalarRegs)
Definition: registers.cc:122
gem5::Gcn3ISA::NumVecElemPerVecReg
const int NumVecElemPerVecReg(64)
gem5::Gcn3ISA::REG_VGPR_MAX
@ REG_VGPR_MAX
Definition: gpu_registers.hh:132
gem5::Gcn3ISA::REG_TTMP_6
@ REG_TTMP_6
Definition: gpu_registers.hh:68
gem5::Gcn3ISA::DWordSize
const int DWordSize
Definition: gpu_registers.hh:172
gem5::Gcn3ISA::REG_TTMP_8
@ REG_TTMP_8
Definition: gpu_registers.hh:70
gem5::Gcn3ISA::NumPosConstRegs
const int NumPosConstRegs
Definition: gpu_registers.hh:138
gem5::Gcn3ISA::REG_RESERVED_18
@ REG_RESERVED_18
Definition: gpu_registers.hh:99
gem5::Gcn3ISA::REG_FLAT_SCRATCH_HI
@ REG_FLAT_SCRATCH_HI
Definition: gpu_registers.hh:53
gem5::Gcn3ISA::VecElemI16
int16_t VecElemI16
Definition: gpu_registers.hh:164
gem5::Gcn3ISA::REG_TTMP_2
@ REG_TTMP_2
Definition: gpu_registers.hh:64
gem5::Gcn3ISA::REG_INT_CONST_POS_MAX
@ REG_INT_CONST_POS_MAX
Definition: gpu_registers.hh:80
gem5::Gcn3ISA::RegSizeDWords
const int RegSizeDWords
Size of a single-precision register in DWords.
Definition: gpu_registers.hh:176
gem5::Gcn3ISA::VecElemF64
double VecElemF64
Definition: gpu_registers.hh:170
gem5::Gcn3ISA::REG_NEG_HALF
@ REG_NEG_HALF
Definition: gpu_registers.hh:115
gem5::Gcn3ISA::StatusReg
Definition: gpu_registers.hh:181
gem5::Gcn3ISA::StatusReg::TTRACE_EN
uint32_t TTRACE_EN
Definition: gpu_registers.hh:197
gem5::Gcn3ISA::REG_TBA_LO
@ REG_TBA_LO
Definition: gpu_registers.hh:58
gem5::Gcn3ISA::VecElemI8
int8_t VecElemI8
Definition: gpu_registers.hh:162
gem5::Gcn3ISA::REG_RESERVED_15
@ REG_RESERVED_15
Definition: gpu_registers.hh:96
gem5::Gcn3ISA::StatusReg::SCC
uint32_t SCC
Definition: gpu_registers.hh:192
gem5::Gcn3ISA::REG_RESERVED_10
@ REG_RESERVED_10
Definition: gpu_registers.hh:91
gem5::Gcn3ISA::REG_RESERVED_12
@ REG_RESERVED_12
Definition: gpu_registers.hh:93
gem5::Gcn3ISA::StatusReg::VCCZ
uint32_t VCCZ
Definition: gpu_registers.hh:200
gem5::Gcn3ISA::ScalarRegU64
uint64_t ScalarRegU64
Definition: gpu_registers.hh:156
gem5::Gcn3ISA::REG_RESERVED_21
@ REG_RESERVED_21
Definition: gpu_registers.hh:102
gem5::Gcn3ISA::REG_XNACK_MASK_LO
@ REG_XNACK_MASK_LO
Definition: gpu_registers.hh:54
gem5::Gcn3ISA::REG_RESERVED_26
@ REG_RESERVED_26
Definition: gpu_registers.hh:107
vec_reg.hh
gem5::Gcn3ISA::REG_RESERVED_1
@ REG_RESERVED_1
Definition: gpu_registers.hh:75
gem5::Gcn3ISA::REG_TMA_HI
@ REG_TMA_HI
Definition: gpu_registers.hh:61
gem5::Gcn3ISA::StatusReg::PERF_EN
uint32_t PERF_EN
Definition: gpu_registers.hh:209
gem5::Gcn3ISA::REG_POS_HALF
@ REG_POS_HALF
Definition: gpu_registers.hh:114
gem5::Gcn3ISA::REG_POS_FOUR
@ REG_POS_FOUR
Definition: gpu_registers.hh:120
gem5::Gcn3ISA::StatusReg::HALT
uint32_t HALT
Definition: gpu_registers.hh:203
gem5::Gcn3ISA::REG_LDS_DIRECT
@ REG_LDS_DIRECT
Definition: gpu_registers.hh:129
gem5::Gcn3ISA::StatusReg::RESERVED_1
uint32_t RESERVED_1
Definition: gpu_registers.hh:216
gem5::Gcn3ISA::MaxOperandDwords
constexpr size_t MaxOperandDwords(16)
gem5::Gcn3ISA::REG_RESERVED_30
@ REG_RESERVED_30
Definition: gpu_registers.hh:111
gem5::Gcn3ISA::REG_TTMP_1
@ REG_TTMP_1
Definition: gpu_registers.hh:63
gem5::Gcn3ISA::REG_RESERVED_32
@ REG_RESERVED_32
Definition: gpu_registers.hh:113
gem5::Gcn3ISA::ScalarRegF64
double ScalarRegF64
Definition: gpu_registers.hh:158
gem5::Gcn3ISA::REG_POS_ONE
@ REG_POS_ONE
Definition: gpu_registers.hh:116
gem5::Gcn3ISA::REG_EXECZ
@ REG_EXECZ
Definition: gpu_registers.hh:127
gem5::Gcn3ISA::REG_TTMP_9
@ REG_TTMP_9
Definition: gpu_registers.hh:71
gem5::Gcn3ISA::StatusReg::TRAP
uint32_t TRAP
Definition: gpu_registers.hh:204
gem5::Gcn3ISA::REG_RESERVED_9
@ REG_RESERVED_9
Definition: gpu_registers.hh:90
gem5::Gcn3ISA::VecElemI64
int64_t VecElemI64
Definition: gpu_registers.hh:169
gem5::Gcn3ISA::REG_SRC_SWDA
@ REG_SRC_SWDA
Definition: gpu_registers.hh:124
gem5::Gcn3ISA::MSB_PER_BYTE
const int MSB_PER_BYTE
Definition: gpu_registers.hh:145
logging.hh
gem5::Gcn3ISA::StatusReg::TTRACE_CU_EN
uint32_t TTRACE_CU_EN
Definition: gpu_registers.hh:205
gem5::Gcn3ISA::BITS_PER_BYTE
const int BITS_PER_BYTE
Definition: gpu_registers.hh:143
gem5::Gcn3ISA::StatusReg::VALID
uint32_t VALID
Definition: gpu_registers.hh:206
gem5::Gcn3ISA::VecElemU8
uint8_t VecElemU8
Definition: gpu_registers.hh:161
gem5::Gcn3ISA::REG_RESERVED_4
@ REG_RESERVED_4
Definition: gpu_registers.hh:85
gem5::Gcn3ISA::REG_RESERVED_23
@ REG_RESERVED_23
Definition: gpu_registers.hh:104
gem5::Gcn3ISA::REG_PI
@ REG_PI
Definition: gpu_registers.hh:122
gem5::Gcn3ISA::StatusReg::INSTRUCTION_ATC
uint32_t INSTRUCTION_ATC
Definition: gpu_registers.hh:213
intmath.hh
gem5::Gcn3ISA::StatusReg::ECC_ERR
uint32_t ECC_ERR
Definition: gpu_registers.hh:207
gem5::Gcn3ISA::REG_TTMP_0
@ REG_TTMP_0
Definition: gpu_registers.hh:62
gem5::Gcn3ISA::VecElemU16
uint16_t VecElemU16
Definition: gpu_registers.hh:163
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::Gcn3ISA::REG_INT_CONST_NEG_MAX
@ REG_INT_CONST_NEG_MAX
Definition: gpu_registers.hh:82
gem5::Gcn3ISA::REG_RESERVED_29
@ REG_RESERVED_29
Definition: gpu_registers.hh:110
gem5::Gcn3ISA::ScalarRegI8
int8_t ScalarRegI8
Definition: gpu_registers.hh:150
gem5::Gcn3ISA::StatusReg::SPI_PRIO
uint32_t SPI_PRIO
Definition: gpu_registers.hh:193
gem5::Gcn3ISA::REG_ZERO
@ REG_ZERO
Definition: gpu_registers.hh:78
gem5::Gcn3ISA::REG_RESERVED_6
@ REG_RESERVED_6
Definition: gpu_registers.hh:87
gem5::Gcn3ISA::REG_RESERVED_2
@ REG_RESERVED_2
Definition: gpu_registers.hh:83
gem5::Gcn3ISA::REG_VCC_HI
@ REG_VCC_HI
Definition: gpu_registers.hh:57
gem5::Gcn3ISA::REG_M0
@ REG_M0
Definition: gpu_registers.hh:74
gem5::Gcn3ISA::isConstVal
bool isConstVal(int opIdx)
Definition: registers.cc:185
gem5::Gcn3ISA::isFlatScratchReg
bool isFlatScratchReg(int opIdx)
Definition: registers.cc:210
gem5::Gcn3ISA::ScalarRegU32
uint32_t ScalarRegU32
Definition: gpu_registers.hh:153
gem5::Gcn3ISA::REG_TTMP_5
@ REG_TTMP_5
Definition: gpu_registers.hh:67
gem5::Gcn3ISA::StatusReg::SKIP_EXPORT
uint32_t SKIP_EXPORT
Definition: gpu_registers.hh:208
gem5::Gcn3ISA::VecElemU64
uint64_t VecElemU64
Definition: gpu_registers.hh:168
gem5::Gcn3ISA::REG_RESERVED_17
@ REG_RESERVED_17
Definition: gpu_registers.hh:98

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