53 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
105 std::stringstream dis_stream;
110 dis_stream <<
"0x" << std::hex << std::setfill(
'0') << std::setw(8)
117 dis_stream <<
"0x" << std::hex << std::setfill(
'0') << std::setw(8)
138 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
193 if (iFmt->
OP == 0x14)
203 std::stringstream dis_stream;
209 dis_stream <<
"0x" << std::hex << std::setfill(
'0')
215 dis_stream <<
"0x" << std::hex << std::setfill(
'0') << std::setw(4)
233 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
283 std::stringstream dis_stream;
288 dis_stream <<
"0x" << std::hex << std::setfill(
'0') << std::setw(8)
309 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
358 std::stringstream dis_stream;
362 dis_stream <<
"0x" << std::hex << std::setfill(
'0') << std::setw(8)
369 dis_stream <<
"0x" << std::hex << std::setfill(
'0') << std::setw(8)
426 std::stringstream dis_stream;
434 dis_stream <<
"label_" << std::hex << dest;
452 dis_stream <<
"vmcnt(" << vm_cnt <<
")";
455 if (lgkm_cnt != 0xf) {
459 dis_stream <<
"lgkmcnt(" << lgkm_cnt <<
")";
462 if (exp_cnt != 0x7) {
463 if (vm_cnt != 0xf || lgkm_cnt != 0xf)
466 dis_stream <<
"expcnt(" << exp_cnt <<
")";
489 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
554 std::stringstream dis_stream;
574 dis_stream <<
"0x" << std::hex << std::setfill(
'0') << std::setw(2)
596 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
676 iFmt->
OP == 0x18 || iFmt->
OP == 0x24 || iFmt->
OP == 0x25)
685 std::stringstream dis_stream;
690 dis_stream <<
"vcc, ";
695 dis_stream <<
"0x" << std::hex << std::setfill(
'0') << std::setw(8)
708 dis_stream <<
"0x" << std::hex << std::setfill(
'0') << std::setw(8)
712 dis_stream << std::resetiosflags(std::ios_base::basefield) <<
"v"
716 dis_stream <<
", vcc";
731 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
798 std::stringstream dis_stream;
805 dis_stream <<
"0x" << std::hex << std::setfill(
'0') << std::setw(8)
825 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
893 std::stringstream dis_stream;
894 dis_stream <<
_opcode <<
" vcc, ";
931 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
949 for (opNum = 0; opNum < numSrc; opNum++) {
987 std::stringstream dis_stream;
998 num_regs - 1 <<
"], ";
1045 const std::string &
opcode)
1052 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
1070 for (opNum = 0; opNum < numSrc; opNum++) {
1078 true,
false,
false);
1086 false,
true,
false);
1092 true,
false,
false);
1108 std::stringstream dis_stream;
1144 dis_stream <<
", vcc";
1160 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
1176 false,
true,
false);
1183 false,
true,
false);
1199 std::stringstream dis_stream;
1224 dis_stream <<
" offset:" <<
offset;
1238 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
1267 false,
true,
false);
1273 false,
true,
false);
1291 false,
true,
false);
1309 std::stringstream dis_stream;
1312 dis_stream <<
"s[" << srsrc_val <<
":"
1313 << srsrc_val + 3 <<
"], ";
1331 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
1358 false,
true,
false);
1364 false,
true,
false);
1381 false,
true,
false);
1403 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
1431 false,
true,
false);
1437 false,
true,
false);
1456 false,
true,
false);
1478 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
1495 for (opNum = 0; opNum < 4; opNum++) {
1497 false,
true,
false);
1519 _srcLiteral = *
reinterpret_cast<uint32_t*
>(&iFmt[1]);
1549 false,
true,
false);
1555 false,
true,
false);
1562 false,
true,
false);
1578 std::stringstream dis_stream;
virtual int numDstRegOperands()=0
std::vector< OperandInfo > srcOps
std::vector< OperandInfo > dstOps
virtual int getNumOperands()=0
const std::string _opcode
virtual int numSrcRegOperands()=0
ScalarRegU32 _srcLiteral
if the instruction has a src literal - an immediate value that is part of the instruction stream - we...
int getOperandSize(int opIdx) override
void generateDisassembly() override
void initOperandInfo() override
Inst_DS(InFmt_DS *, const std::string &opcode)
int instSize() const override
Inst_EXP(InFmt_EXP *, const std::string &opcode)
int instSize() const override
void initOperandInfo() override
Inst_FLAT(InFmt_FLAT *, const std::string &opcode)
int instSize() const override
void generateDisassembly() override
void initOperandInfo() override
int instSize() const override
void initOperandInfo() override
Inst_MIMG(InFmt_MIMG *, const std::string &opcode)
Inst_MTBUF(InFmt_MTBUF *, const std::string &opcode)
void initOperandInfo() override
int instSize() const override
void initOperandInfo() override
Inst_MUBUF(InFmt_MUBUF *, const std::string &opcode)
int instSize() const override
void generateDisassembly() override
void generateDisassembly() override
Inst_SMEM(InFmt_SMEM *, const std::string &opcode)
void initOperandInfo() override
int instSize() const override
Inst_SOP1(InFmt_SOP1 *, const std::string &opcode)
int instSize() const override
bool hasSecondDword(InFmt_SOP1 *)
void initOperandInfo() override
void generateDisassembly() override
bool hasSecondDword(InFmt_SOP2 *)
void generateDisassembly() override
Inst_SOP2(InFmt_SOP2 *, const std::string &opcode)
void initOperandInfo() override
int instSize() const override
bool hasSecondDword(InFmt_SOPC *)
int instSize() const override
void initOperandInfo() override
Inst_SOPC(InFmt_SOPC *, const std::string &opcode)
void generateDisassembly() override
int instSize() const override
void generateDisassembly() override
Inst_SOPK(InFmt_SOPK *, const std::string &opcode)
bool hasSecondDword(InFmt_SOPK *)
void initOperandInfo() override
Inst_SOPP(InFmt_SOPP *, const std::string &opcode)
void initOperandInfo() override
void generateDisassembly() override
int instSize() const override
int instSize() const override
Inst_VINTRP(InFmt_VINTRP *, const std::string &opcode)
void generateDisassembly() override
int instSize() const override
Inst_VOP1(InFmt_VOP1 *, const std::string &opcode)
void initOperandInfo() override
bool hasSecondDword(InFmt_VOP1 *)
int instSize() const override
void initOperandInfo() override
Inst_VOP2(InFmt_VOP2 *, const std::string &opcode)
void generateDisassembly() override
bool hasSecondDword(InFmt_VOP2 *)
void initOperandInfo() override
int instSize() const override
InFmt_VOP3_SDST_ENC instData
Inst_VOP3_SDST_ENC(InFmt_VOP3_SDST_ENC *, const std::string &opcode)
void generateDisassembly() override
void initOperandInfo() override
const bool sgprDst
the v_cmp and readlane instructions in the VOP3 encoding are unique because they are the only instruc...
int instSize() const override
void generateDisassembly() override
Inst_VOP3(InFmt_VOP3 *, const std::string &opcode, bool sgpr_dst)
bool hasSecondDword(InFmt_VOPC *)
void initOperandInfo() override
void generateDisassembly() override
Inst_VOPC(InFmt_VOPC *, const std::string &opcode)
int instSize() const override
This is a simple scalar statistic, like a counter.
Bitfield< 24, 21 > opcode
InstFormat * MachInst
used to represent the encoding of a GCN3 inst.
std::string opSelectorToRegSym(int opIdx, int numRegs=0)
bool isScalarReg(int opIdx)
bool isVectorReg(int opIdx)
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....