gem5  v21.1.0.2
op_encodings.cc
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1 /*
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33 
35 
36 #include <iomanip>
37 
38 namespace gem5
39 {
40 
41 namespace Gcn3ISA
42 {
43  // --- Inst_SOP2 base class methods ---
44 
45  Inst_SOP2::Inst_SOP2(InFmt_SOP2 *iFmt, const std::string &opcode)
47  {
48  setFlag(Scalar);
49 
50  // copy first instruction DWORD
51  instData = iFmt[0];
52  if (hasSecondDword(iFmt)) {
53  // copy second instruction DWORD into union
54  extData = ((MachInst)iFmt)[1];
55  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
56  varSize = 4 + 4;
57  } else {
58  varSize = 4;
59  } // if
60  } // Inst_SOP2
61 
62  void
64  {
65  int opNum = 0;
66 
67  // Needed because can't take addr of bitfield
68  int reg = instData.SSRC0;
69  srcOps.emplace_back(reg, getOperandSize(opNum), true,
70  isScalarReg(instData.SSRC0), false, false);
71  opNum++;
72 
73  reg = instData.SSRC1;
74  srcOps.emplace_back(reg, getOperandSize(opNum), true,
75  isScalarReg(instData.SSRC1), false, false);
76  opNum++;
77 
78  reg = instData.SDST;
79  dstOps.emplace_back(reg, getOperandSize(opNum), false,
80  isScalarReg(instData.SDST), false, false);
81 
82  assert(srcOps.size() == numSrcRegOperands());
83  assert(dstOps.size() == numDstRegOperands());
84  }
85 
86  int
88  {
89  return varSize;
90  } // instSize
91 
92  bool
94  {
95  if (iFmt->SSRC0 == REG_SRC_LITERAL)
96  return true;
97 
98  if (iFmt->SSRC1 == REG_SRC_LITERAL)
99  return true;
100 
101  return false;
102  }
103 
104  void
106  {
107  std::stringstream dis_stream;
108  dis_stream << _opcode << " ";
109  dis_stream << opSelectorToRegSym(instData.SDST) << ", ";
110 
111  if (instData.SSRC0 == REG_SRC_LITERAL) {
112  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
113  << _srcLiteral << ", ";
114  } else {
115  dis_stream << opSelectorToRegSym(instData.SSRC0) << ", ";
116  }
117 
118  if (instData.SSRC1 == REG_SRC_LITERAL) {
119  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
120  << _srcLiteral;
121  } else {
122  dis_stream << opSelectorToRegSym(instData.SSRC1);
123  }
124 
125  disassembly = dis_stream.str();
126  }
127 
128  // --- Inst_SOPK base class methods ---
129 
130  Inst_SOPK::Inst_SOPK(InFmt_SOPK *iFmt, const std::string &opcode)
132  {
133  setFlag(Scalar);
134 
135  // copy first instruction DWORD
136  instData = iFmt[0];
137  if (hasSecondDword(iFmt)) {
138  // copy second instruction DWORD into union
139  extData = ((MachInst)iFmt)[1];
140  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
141  varSize = 4 + 4;
142  } else {
143  varSize = 4;
144  } // if
145  } // Inst_SOPK
146 
148  {
149  } // ~Inst_SOPK
150 
151  void
153  {
154  int opNum = 0;
155 
156  // Needed because can't take addr of bitfield
157  int reg = instData.SDST;
158  if (numSrcRegOperands() == getNumOperands()) {
159  srcOps.emplace_back(reg, getOperandSize(opNum), true,
160  isScalarReg(reg), false, false);
161  opNum++;
162  }
163 
164  reg = instData.SIMM16;
165  srcOps.emplace_back(reg, getOperandSize(opNum), true,
166  false, false, true);
167  opNum++;
168 
169  if (numDstRegOperands()){
170  reg = instData.SDST;
171  dstOps.emplace_back(reg, getOperandSize(opNum), false,
172  isScalarReg(reg), false, false);
173  }
174 
175  assert(srcOps.size() == numSrcRegOperands());
176  assert(dstOps.size() == numDstRegOperands());
177  }
178 
179  int
181  {
182  return varSize;
183  } // instSize
184 
185  bool
187  {
188  /*
189  SOPK can be a 64-bit instruction, i.e., have a second dword:
190  S_SETREG_IMM32_B32 writes some or all of the LSBs of a 32-bit
191  literal constant into a hardware register;
192  the way to detect such special case is to explicitly check the
193  opcode (20/0x14)
194  */
195  if (iFmt->OP == 0x14)
196  return true;
197 
198  return false;
199  }
200 
201 
202  void
204  {
205  std::stringstream dis_stream;
206  dis_stream << _opcode << " ";
207 
208  // S_SETREG_IMM32_B32 is a 64-bit instruction, using a
209  // 32-bit literal constant
210  if (instData.OP == 0x14) {
211  dis_stream << "0x" << std::hex << std::setfill('0')
212  << std::setw(8) << extData.imm_u32 << ", ";
213  } else {
214  dis_stream << opSelectorToRegSym(instData.SDST) << ", ";
215  }
216 
217  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(4)
218  << instData.SIMM16;
219 
220  disassembly = dis_stream.str();
221  }
222 
223  // --- Inst_SOP1 base class methods ---
224 
225  Inst_SOP1::Inst_SOP1(InFmt_SOP1 *iFmt, const std::string &opcode)
227  {
228  setFlag(Scalar);
229 
230  // copy first instruction DWORD
231  instData = iFmt[0];
232  if (hasSecondDword(iFmt)) {
233  // copy second instruction DWORD into union
234  extData = ((MachInst)iFmt)[1];
235  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
236  varSize = 4 + 4;
237  } else {
238  varSize = 4;
239  } // if
240  } // Inst_SOP1
241 
243  {
244  } // ~Inst_SOP1
245 
246  void
248  {
249  int opNum = 0;
250 
251  // Needed because can't take addr of bitfield
252  int reg = instData.SSRC0;
253  if (instData.OP != 0x1C) {
254  srcOps.emplace_back(reg, getOperandSize(opNum), true,
255  isScalarReg(instData.SSRC0), false, false);
256  opNum++;
257  }
258 
259  reg = instData.SDST;
260  dstOps.emplace_back(reg, getOperandSize(opNum), false,
261  isScalarReg(instData.SDST), false, false);
262 
263  assert(srcOps.size() == numSrcRegOperands());
264  assert(dstOps.size() == numDstRegOperands());
265  }
266 
267  int
269  {
270  return varSize;
271  } // instSize
272 
273  bool
275  {
276  if (iFmt->SSRC0 == REG_SRC_LITERAL)
277  return true;
278 
279  return false;
280  }
281 
282  void
284  {
285  std::stringstream dis_stream;
286  dis_stream << _opcode << " ";
287  dis_stream << opSelectorToRegSym(instData.SDST) << ", ";
288 
289  if (instData.SSRC0 == REG_SRC_LITERAL) {
290  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
291  << extData.imm_u32;
292  } else {
293  dis_stream << opSelectorToRegSym(instData.SSRC0);
294  }
295 
296  disassembly = dis_stream.str();
297  }
298 
299  // --- Inst_SOPC base class methods ---
300 
301  Inst_SOPC::Inst_SOPC(InFmt_SOPC *iFmt, const std::string &opcode)
303  {
304  setFlag(Scalar);
305 
306  // copy first instruction DWORD
307  instData = iFmt[0];
308  if (hasSecondDword(iFmt)) {
309  // copy second instruction DWORD into union
310  extData = ((MachInst)iFmt)[1];
311  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
312  varSize = 4 + 4;
313  } else {
314  varSize = 4;
315  } // if
316  } // Inst_SOPC
317 
319  {
320  } // ~Inst_SOPC
321 
322  void
324  {
325  int opNum = 0;
326 
327  // Needed because can't take addr of bitfield
328  int reg = instData.SSRC0;
329  srcOps.emplace_back(reg, getOperandSize(opNum), true,
330  isScalarReg(instData.SSRC0), false, false);
331  opNum++;
332 
333  reg = instData.SSRC1;
334  srcOps.emplace_back(reg, getOperandSize(opNum), true,
335  isScalarReg(instData.SSRC1), false, false);
336 
337  }
338 
339  int
341  {
342  return varSize;
343  } // instSize
344 
345  bool
347  {
348  if (iFmt->SSRC0 == REG_SRC_LITERAL)
349  return true;
350 
351  if (iFmt->SSRC1 == REG_SRC_LITERAL)
352  return true;
353 
354  return false;
355  }
356 
357  void
359  {
360  std::stringstream dis_stream;
361  dis_stream << _opcode << " ";
362 
363  if (instData.SSRC0 == REG_SRC_LITERAL) {
364  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
365  << extData.imm_u32;
366  } else {
367  dis_stream << opSelectorToRegSym(instData.SSRC0) << ", ";
368  }
369 
370  if (instData.SSRC1 == REG_SRC_LITERAL) {
371  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
372  << extData.imm_u32;
373  } else {
374  dis_stream << opSelectorToRegSym(instData.SSRC1);
375  }
376 
377  disassembly = dis_stream.str();
378  }
379 
380  // --- Inst_SOPP base class methods ---
381 
382  Inst_SOPP::Inst_SOPP(InFmt_SOPP *iFmt, const std::string &opcode)
384  {
385  setFlag(Scalar);
386 
387  // copy first instruction DWORD
388  instData = iFmt[0];
389  } // Inst_SOPP
390 
392  {
393  } // ~Inst_SOPP
394 
395  void
397  {
398  int opNum = 0;
399 
400 
401  if (numSrcRegOperands()) {
402  // Needed because can't take addr of bitfield
403  int reg = instData.SIMM16;
404  srcOps.emplace_back(reg, getOperandSize(opNum), true,
405  false, false, true);
406 
407  opNum++;
408 
409  if (readsVCC()) {
410  srcOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), true,
411  true, false, false);
412  opNum++;
413  }
414  }
415  assert(srcOps.size() == numSrcRegOperands());
416  assert(dstOps.size() == numDstRegOperands());
417  }
418 
419  int
421  {
422  return 4;
423  } // instSize
424 
425  void
427  {
428  std::stringstream dis_stream;
429  dis_stream << _opcode;
430 
431  switch (instData.OP) {
432  case 8:
433  {
434  dis_stream << " ";
435  int dest = 4 * instData.SIMM16 + 4;
436  dis_stream << "label_" << std::hex << dest;
437  }
438  break;
439  case 12:
440  {
441  dis_stream << " ";
442 
443  int vm_cnt = 0;
444  int exp_cnt = 0;
445  int lgkm_cnt = 0;
446 
447  vm_cnt = bits<uint16_t>(instData.SIMM16, 3, 0);
448  exp_cnt = bits<uint16_t>(instData.SIMM16, 6, 4);
449  lgkm_cnt = bits<uint16_t>(instData.SIMM16, 11, 8);
450 
451  // if the counts are not maxed out, then we
452  // print out the count value
453  if (vm_cnt != 0xf) {
454  dis_stream << "vmcnt(" << vm_cnt << ")";
455  }
456 
457  if (lgkm_cnt != 0xf) {
458  if (vm_cnt != 0xf)
459  dis_stream << " & ";
460 
461  dis_stream << "lgkmcnt(" << lgkm_cnt << ")";
462  }
463 
464  if (exp_cnt != 0x7) {
465  if (vm_cnt != 0xf || lgkm_cnt != 0xf)
466  dis_stream << " & ";
467 
468  dis_stream << "expcnt(" << exp_cnt << ")";
469  }
470  }
471  break;
472  default:
473  break;
474  }
475 
476  disassembly = dis_stream.str();
477  }
478 
479  // --- Inst_SMEM base class methods ---
480 
481  Inst_SMEM::Inst_SMEM(InFmt_SMEM *iFmt, const std::string &opcode)
483  {
484  setFlag(Scalar);
485  setFlag(GlobalSegment);
486 
487  // copy first instruction DWORD
488  instData = iFmt[0];
489  // copy second instruction DWORD
490  extData = ((InFmt_SMEM_1 *)iFmt)[1];
491  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
492 
493  if (instData.GLC)
494  setFlag(GloballyCoherent);
495  } // Inst_SMEM
496 
498  {
499  } // ~Inst_SMEM
500 
501  void
503  {
504  // Formats:
505  // 0 src + 0 dst
506  // 3 src + 0 dst
507  // 2 src + 1 dst
508  // 0 src + 1 dst
509  int opNum = 0;
510  // Needed because can't take addr of bitfield
511  int reg = 0;
512 
513  if (numSrcRegOperands()) {
514  reg = instData.SDATA;
515  if (numSrcRegOperands() == getNumOperands()) {
516  srcOps.emplace_back(reg, getOperandSize(opNum), true,
517  isScalarReg(reg), false, false);
518  opNum++;
519  }
520 
521  reg = instData.SBASE;
522  srcOps.emplace_back(reg, getOperandSize(opNum), true,
523  true, false, false);
524  opNum++;
525 
526  reg = extData.OFFSET;
527  if (instData.IMM) {
528  srcOps.emplace_back(reg, getOperandSize(opNum), true,
529  false, false, true);
530  } else {
531  srcOps.emplace_back(reg, getOperandSize(opNum), true,
532  isScalarReg(reg), false, false);
533  }
534  opNum++;
535  }
536 
537  if (numDstRegOperands()) {
538  reg = instData.SDATA;
539  dstOps.emplace_back(reg, getOperandSize(opNum), false,
540  isScalarReg(reg), false, false);
541  }
542 
543  assert(srcOps.size() == numSrcRegOperands());
544  assert(dstOps.size() == numDstRegOperands());
545  }
546 
547  int
549  {
550  return 8;
551  } // instSize
552 
553  void
555  {
556  std::stringstream dis_stream;
557  dis_stream << _opcode << " ";
558  if (numDstRegOperands()) {
559  if (getOperandSize(getNumOperands() - 1) > 4) {
560  dis_stream << "s[" << instData.SDATA << ":"
562  4 - 1 << "], ";
563  } else {
564  dis_stream << "s" << instData.SDATA << ", ";
565  }
566  }
567 
568  // SBASE has an implied LSB of 0, so we need
569  // to shift by one to get the actual value
570  dis_stream << "s[" << (instData.SBASE << 1) << ":"
571  << ((instData.SBASE << 1) + 1) << "], ";
572 
573  if (instData.IMM) {
574  // IMM == 1 implies OFFSET should be
575  // used as the offset
576  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(2)
577  << extData.OFFSET;
578  } else {
579  // IMM == 0 implies OFFSET should be
580  // used to specify SGRP in which the
581  // offset is held
582  dis_stream << "s" << extData.OFFSET;
583  }
584 
585  disassembly = dis_stream.str();
586  }
587 
588  // --- Inst_VOP2 base class methods ---
589 
590  Inst_VOP2::Inst_VOP2(InFmt_VOP2 *iFmt, const std::string &opcode)
592  {
593  // copy first instruction DWORD
594  instData = iFmt[0];
595  if (hasSecondDword(iFmt)) {
596  // copy second instruction DWORD into union
597  extData = ((MachInst)iFmt)[1];
598  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
599  varSize = 4 + 4;
600  if (iFmt->SRC0 == REG_SRC_DPP) {
601  setFlag(IsDPP);
602  } else if (iFmt->SRC0 == REG_SRC_SWDA) {
603  setFlag(IsSDWA);
604  }
605  } else {
606  varSize = 4;
607  } // if
608  } // Inst_VOP2
609 
611  {
612  } // ~Inst_VOP2
613 
614  void
616  {
617  int opNum = 0;
618 
619  // Needed because can't take addr of bitfield
620  int reg = instData.SRC0;
621  srcOps.emplace_back(reg, getOperandSize(opNum), true,
622  isScalarReg(reg), isVectorReg(reg), false);
623  opNum++;
624 
625  reg = instData.VSRC1;
626  srcOps.emplace_back(reg, getOperandSize(opNum), true,
627  false, true, false);
628  opNum++;
629 
630  // VCC read
631  if (readsVCC()) {
632  srcOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), true,
633  true, false, false);
634  opNum++;
635  }
636 
637  // VDST
638  reg = instData.VDST;
639  dstOps.emplace_back(reg, getOperandSize(opNum), false,
640  false, true, false);
641  opNum++;
642 
643  // VCC write
644  if (writesVCC()) {
645  dstOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), false,
646  true, false, false);
647  }
648 
649  assert(srcOps.size() == numSrcRegOperands());
650  assert(dstOps.size() == numDstRegOperands());
651  }
652 
653  int
655  {
656  return varSize;
657  } // instSize
658 
659  bool
661  {
662  /*
663  There are a few cases where VOP2 instructions have a second dword:
664 
665  1. SRC0 is a literal
666  2. SRC0 is being used to add a data parallel primitive (DPP)
667  operation to the instruction.
668  3. SRC0 is being used for sub d-word addressing (SDWA) of the
669  operands in the instruction.
670  4. VOP2 instructions also have four special opcodes:',
671  V_MADMK_{F16, F32} (0x24, 0x17), and V_MADAK_{F16, F32}',
672  (0x25, 0x18), that are always 64b. the only way to',
673  detect these special cases is to explicitly check,',
674  the opcodes',
675  */
676  if (iFmt->SRC0 == REG_SRC_LITERAL || (iFmt->SRC0 == REG_SRC_DPP) ||
677  (iFmt->SRC0 == REG_SRC_SWDA) || iFmt->OP == 0x17 ||
678  iFmt->OP == 0x18 || iFmt->OP == 0x24 || iFmt->OP == 0x25)
679  return true;
680 
681  return false;
682  }
683 
684  void
686  {
687  std::stringstream dis_stream;
688  dis_stream << _opcode << " ";
689  dis_stream << "v" << instData.VDST << ", ";
690 
691  if (writesVCC())
692  dis_stream << "vcc, ";
693 
694  if ((instData.SRC0 == REG_SRC_LITERAL) ||
695  (instData.SRC0 == REG_SRC_DPP) ||
696  (instData.SRC0 == REG_SRC_SWDA)) {
697  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
698  << _srcLiteral << ", ";
699  } else {
700  dis_stream << opSelectorToRegSym(instData.SRC0) << ", ";
701  }
702 
703  // VOP2 instructions have four special opcodes:',
704  // V_MADMK_{F16, F32} (0x24, 0x17), and V_MADAK_{F16, F32}',
705  // (0x25, 0x18), that are always 64b. the only way to',
706  // detect these special cases is to explicitly check,',
707  // the opcodes',
708  if (instData.OP == 0x17 || instData.OP == 0x18 || instData.OP == 0x24
709  || instData.OP == 0x25) {
710  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
711  << extData.imm_u32 << ", ";
712  }
713 
714  dis_stream << std::resetiosflags(std::ios_base::basefield) << "v"
715  << instData.VSRC1;
716 
717  if (readsVCC())
718  dis_stream << ", vcc";
719 
720  disassembly = dis_stream.str();
721  }
722 
723  // --- Inst_VOP1 base class methods ---
724 
725  Inst_VOP1::Inst_VOP1(InFmt_VOP1 *iFmt, const std::string &opcode)
727  {
728  // copy first instruction DWORD
729  instData = iFmt[0];
730  if (hasSecondDword(iFmt)) {
731  // copy second instruction DWORD into union
732  extData = ((MachInst)iFmt)[1];
733  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
734  varSize = 4 + 4;
735  if (iFmt->SRC0 == REG_SRC_DPP) {
736  setFlag(IsDPP);
737  } else if (iFmt->SRC0 == REG_SRC_SWDA) {
738  setFlag(IsSDWA);
739  }
740  } else {
741  varSize = 4;
742  } // if
743  } // Inst_VOP1
744 
746  {
747  } // ~Inst_VOP1
748 
749  void
751  {
752  int opNum = 0;
753  // Needed because can't take addr of bitfield
754  int reg = instData.SRC0;
755 
756  if (numSrcRegOperands()) {
757  srcOps.emplace_back(reg, getOperandSize(opNum), true,
758  isScalarReg(reg), isVectorReg(reg), false);
759  opNum++;
760  }
761 
762  if (numDstRegOperands()) {
763  reg = instData.VDST;
764  dstOps.emplace_back(reg, getOperandSize(opNum), false,
765  false, true, false);
766  }
767 
768  assert(srcOps.size() == numSrcRegOperands());
769  assert(dstOps.size() == numDstRegOperands());
770  }
771 
772  int
774  {
775  return varSize;
776  } // instSize
777 
778  bool
780  {
781  /*
782  There are several cases where VOP1 instructions have a second dword:
783 
784  1. SRC0 is a literal.
785  2. SRC0 is being used to add a data parallel primitive (DPP)
786  operation to the instruction.
787  3. SRC0 is being used for sub d-word addressing (SDWA) of the
788  operands in the instruction.
789  */
790  if ((iFmt->SRC0 == REG_SRC_LITERAL) || (iFmt->SRC0 == REG_SRC_DPP) ||
791  (iFmt->SRC0 == REG_SRC_SWDA))
792  return true;
793 
794  return false;
795  }
796 
797  void
799  {
800  std::stringstream dis_stream;
801  dis_stream << _opcode << " ";
802  dis_stream << "v" << instData.VDST << ", ";
803 
804  if ((instData.SRC0 == REG_SRC_LITERAL) ||
805  (instData.SRC0 == REG_SRC_DPP) ||
806  (instData.SRC0 == REG_SRC_SWDA)) {
807  dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(8)
808  << _srcLiteral;
809  } else {
810  dis_stream << opSelectorToRegSym(instData.SRC0);
811  }
812 
813  disassembly = dis_stream.str();
814  }
815 
816  // --- Inst_VOPC base class methods ---
817 
818  Inst_VOPC::Inst_VOPC(InFmt_VOPC *iFmt, const std::string &opcode)
820  {
821  setFlag(WritesVCC);
822  // copy first instruction DWORD
823  instData = iFmt[0];
824  if (hasSecondDword(iFmt)) {
825  // copy second instruction DWORD into union
826  extData = ((MachInst)iFmt)[1];
827  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
828  varSize = 4 + 4;
829  if (iFmt->SRC0 == REG_SRC_DPP) {
830  setFlag(IsDPP);
831  } else if (iFmt->SRC0 == REG_SRC_SWDA) {
832  setFlag(IsSDWA);
833  }
834  } else {
835  varSize = 4;
836  } // if
837  } // Inst_VOPC
838 
840  {
841  } // ~Inst_VOPC
842 
843  void
845  {
846  int opNum = 0;
847 
848  // Needed because can't take addr of bitfield
849  int reg = instData.SRC0;
850  srcOps.emplace_back(reg, getOperandSize(opNum), true,
851  isScalarReg(reg), isVectorReg(reg), false);
852  opNum++;
853 
854  reg = instData.VSRC1;
855  srcOps.emplace_back(reg, getOperandSize(opNum), true,
856  false, true, false);
857  opNum++;
858 
859  assert(writesVCC());
860  dstOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), false,
861  true, false, false);
862 
863  assert(srcOps.size() == numSrcRegOperands());
864  assert(dstOps.size() == numDstRegOperands());
865  }
866 
867  int
869  {
870  return varSize;
871  } // instSize
872 
873  bool
875  {
876  /*
877  There are several cases where VOPC instructions have a second dword:
878 
879  1. SRC0 is a literal.
880  2. SRC0 is being used to add a data parallel primitive (DPP)
881  operation to the instruction.
882  3. SRC0 is being used for sub d-word addressing (SDWA) of the
883  operands in the instruction.
884  */
885  if ((iFmt->SRC0 == REG_SRC_LITERAL) || (iFmt->SRC0 == REG_SRC_DPP) ||
886  (iFmt->SRC0 == REG_SRC_SWDA))
887  return true;
888 
889  return false;
890  }
891 
892  void
894  {
895  std::stringstream dis_stream;
896  dis_stream << _opcode << " vcc, ";
897 
898  dis_stream << opSelectorToRegSym(instData.SRC0) << ", ";
899  dis_stream << "v" << instData.VSRC1;
900 
901  disassembly = dis_stream.str();
902  }
903 
904  // --- Inst_VINTRP base class methods ---
905 
906  Inst_VINTRP::Inst_VINTRP(InFmt_VINTRP *iFmt, const std::string &opcode)
908  {
909  // copy first instruction DWORD
910  instData = iFmt[0];
911  } // Inst_VINTRP
912 
914  {
915  } // ~Inst_VINTRP
916 
917  int
919  {
920  return 4;
921  } // instSize
922 
923  // --- Inst_VOP3 base class methods ---
924 
925  Inst_VOP3::Inst_VOP3(InFmt_VOP3 *iFmt, const std::string &opcode,
926  bool sgpr_dst)
927  : GCN3GPUStaticInst(opcode), sgprDst(sgpr_dst)
928  {
929  // copy first instruction DWORD
930  instData = iFmt[0];
931  // copy second instruction DWORD
932  extData = ((InFmt_VOP3_1 *)iFmt)[1];
933  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
934  } // Inst_VOP3
935 
937  {
938  } // ~Inst_VOP3
939 
940  void
942  {
943  // Also takes care of bitfield addr issue
944  unsigned int srcs[3] = {extData.SRC0, extData.SRC1, extData.SRC2};
945 
946  int opNum = 0;
947 
948  int numSrc = numSrcRegOperands() - readsVCC();
949  int numDst = numDstRegOperands() - writesVCC();
950 
951  for (opNum = 0; opNum < numSrc; opNum++) {
952  srcOps.emplace_back(srcs[opNum], getOperandSize(opNum), true,
953  isScalarReg(srcs[opNum]),
954  isVectorReg(srcs[opNum]), false);
955  }
956 
957  if (readsVCC()) {
958  srcOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), true,
959  true, false, false);
960  opNum++;
961  }
962 
963  if (numDst) {
964  // Needed because can't take addr of bitfield
965  int reg = instData.VDST;
966  dstOps.emplace_back(reg, getOperandSize(opNum), false,
967  sgprDst, !sgprDst, false);
968  opNum++;
969  }
970 
971  if (writesVCC()) {
972  dstOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), false,
973  true, false, false);
974  }
975 
976  assert(srcOps.size() == numSrcRegOperands());
977  assert(dstOps.size() == numDstRegOperands());
978  }
979 
980  int
982  {
983  return 8;
984  } // instSize
985 
986  void
988  {
989  std::stringstream dis_stream;
990  dis_stream << _opcode << " ";
991  int num_regs = 0;
992 
993  if (getOperandSize(getNumOperands() - 1) > 4) {
994  num_regs = getOperandSize(getNumOperands() - 1) / 4;
995  if (sgprDst)
996  dis_stream << "s[";
997  else
998  dis_stream << "v[";
999  dis_stream << instData.VDST << ":" << instData.VDST +
1000  num_regs - 1 << "], ";
1001  } else {
1002  if (sgprDst)
1003  dis_stream << "s";
1004  else
1005  dis_stream << "v";
1006  dis_stream << instData.VDST << ", ";
1007  }
1008 
1009  num_regs = getOperandSize(0) / 4;
1010 
1011  if (extData.NEG & 0x1) {
1012  dis_stream << "-" << opSelectorToRegSym(extData.SRC0, num_regs);
1013  } else {
1014  dis_stream << opSelectorToRegSym(extData.SRC0, num_regs);
1015  }
1016 
1017  if (numSrcRegOperands() > 1) {
1018  num_regs = getOperandSize(1) / 4;
1019 
1020  if (extData.NEG & 0x2) {
1021  dis_stream << ", -"
1022  << opSelectorToRegSym(extData.SRC1, num_regs);
1023  } else {
1024  dis_stream << ", "
1025  << opSelectorToRegSym(extData.SRC1, num_regs);
1026  }
1027  }
1028 
1029  if (numSrcRegOperands() > 2) {
1030  num_regs = getOperandSize(2) / 4;
1031 
1032  if (extData.NEG & 0x4) {
1033  dis_stream << ", -"
1034  << opSelectorToRegSym(extData.SRC2, num_regs);
1035  } else {
1036  dis_stream << ", "
1037  << opSelectorToRegSym(extData.SRC2, num_regs);
1038  }
1039  }
1040 
1041  disassembly = dis_stream.str();
1042  }
1043 
1044  // --- Inst_VOP3_SDST_ENC base class methods ---
1045 
1047  const std::string &opcode)
1049  {
1050  // copy first instruction DWORD
1051  instData = iFmt[0];
1052  // copy second instruction DWORD
1053  extData = ((InFmt_VOP3_1 *)iFmt)[1];
1054  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
1055  } // Inst_VOP3_SDST_ENC
1056 
1058  {
1059  } // ~Inst_VOP3_SDST_ENC
1060 
1061  void
1063  {
1064  // Also takes care of bitfield addr issue
1065  unsigned int srcs[3] = {extData.SRC0, extData.SRC1, extData.SRC2};
1066 
1067  int opNum = 0;
1068 
1069  int numSrc = numSrcRegOperands() - readsVCC();
1070  int numDst = numDstRegOperands() - writesVCC();
1071 
1072  for (opNum = 0; opNum < numSrc; opNum++) {
1073  srcOps.emplace_back(srcs[opNum], getOperandSize(opNum), true,
1074  isScalarReg(srcs[opNum]),
1075  isVectorReg(srcs[opNum]), false);
1076  }
1077 
1078  if (readsVCC()) {
1079  srcOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), true,
1080  true, false, false);
1081  opNum++;
1082  }
1083 
1084  if (numDst) {
1085  // Needed because can't take addr of bitfield
1086  int reg = instData.VDST;
1087  dstOps.emplace_back(reg, getOperandSize(opNum), false,
1088  false, true, false);
1089  opNum++;
1090  }
1091 
1092  if (writesVCC()) {
1093  dstOps.emplace_back(REG_VCC_LO, getOperandSize(opNum), false,
1094  true, false, false);
1095  }
1096 
1097  assert(srcOps.size() == numSrcRegOperands());
1098  assert(dstOps.size() == numDstRegOperands());
1099  }
1100 
1101  int
1103  {
1104  return 8;
1105  } // instSize
1106 
1107  void
1109  {
1110  std::stringstream dis_stream;
1111  dis_stream << _opcode << " ";
1112 
1113  dis_stream << "v" << instData.VDST << ", ";
1114 
1115  if (numDstRegOperands() == 2) {
1116  if (getOperandSize(getNumOperands() - 1) > 4) {
1117  int num_regs = getOperandSize(getNumOperands() - 1) / 4;
1118  dis_stream << opSelectorToRegSym(instData.SDST, num_regs)
1119  << ", ";
1120  } else {
1121  dis_stream << opSelectorToRegSym(instData.SDST) << ", ";
1122  }
1123  }
1124 
1125  if (extData.NEG & 0x1) {
1126  dis_stream << "-" << opSelectorToRegSym(extData.SRC0) << ", ";
1127  } else {
1128  dis_stream << opSelectorToRegSym(extData.SRC0) << ", ";
1129  }
1130 
1131  if (extData.NEG & 0x2) {
1132  dis_stream << "-" << opSelectorToRegSym(extData.SRC1);
1133  } else {
1134  dis_stream << opSelectorToRegSym(extData.SRC1);
1135  }
1136 
1137  if (numSrcRegOperands() == 3) {
1138  if (extData.NEG & 0x4) {
1139  dis_stream << ", -" << opSelectorToRegSym(extData.SRC2);
1140  } else {
1141  dis_stream << ", " << opSelectorToRegSym(extData.SRC2);
1142  }
1143  }
1144 
1145  if (readsVCC())
1146  dis_stream << ", vcc";
1147 
1148  disassembly = dis_stream.str();
1149  }
1150 
1151  // --- Inst_DS base class methods ---
1152 
1153  Inst_DS::Inst_DS(InFmt_DS *iFmt, const std::string &opcode)
1155  {
1156  setFlag(GroupSegment);
1157 
1158  // copy first instruction DWORD
1159  instData = iFmt[0];
1160  // copy second instruction DWORD
1161  extData = ((InFmt_DS_1 *)iFmt)[1];
1162  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
1163  } // Inst_DS
1164 
1166  {
1167  } // ~Inst_DS
1168 
1169  void
1171  {
1172  unsigned int srcs[3] = {extData.ADDR, extData.DATA0, extData.DATA1};
1173 
1174  int opIdx = 0;
1175 
1176  for (opIdx = 0; opIdx < numSrcRegOperands(); opIdx++){
1177  srcOps.emplace_back(srcs[opIdx], getOperandSize(opIdx), true,
1178  false, true, false);
1179  }
1180 
1181  if (numDstRegOperands()) {
1182  // Needed because can't take addr of bitfield
1183  int reg = extData.VDST;
1184  dstOps.emplace_back(reg, getOperandSize(opIdx), false,
1185  false, true, false);
1186  }
1187 
1188  assert(srcOps.size() == numSrcRegOperands());
1189  assert(dstOps.size() == numDstRegOperands());
1190  }
1191 
1192  int
1194  {
1195  return 8;
1196  } // instSize
1197 
1198  void
1200  {
1201  std::stringstream dis_stream;
1202  dis_stream << _opcode << " ";
1203 
1204  if (numDstRegOperands())
1205  dis_stream << "v" << extData.VDST << ", ";
1206 
1207  dis_stream << "v" << extData.ADDR;
1208 
1209  if (numSrcRegOperands() > 1)
1210  dis_stream << ", v" << extData.DATA0;
1211 
1212  if (numSrcRegOperands() > 2)
1213  dis_stream << ", v" << extData.DATA1;
1214 
1215  uint16_t offset = 0;
1216 
1217  if (instData.OFFSET1) {
1218  offset += instData.OFFSET1;
1219  offset <<= 8;
1220  }
1221 
1222  if (instData.OFFSET0)
1223  offset += instData.OFFSET0;
1224 
1225  if (offset)
1226  dis_stream << " offset:" << offset;
1227 
1228  disassembly = dis_stream.str();
1229  }
1230 
1231  // --- Inst_MUBUF base class methods ---
1232 
1233  Inst_MUBUF::Inst_MUBUF(InFmt_MUBUF *iFmt, const std::string &opcode)
1235  {
1236  // copy first instruction DWORD
1237  instData = iFmt[0];
1238  // copy second instruction DWORD
1239  extData = ((InFmt_MUBUF_1 *)iFmt)[1];
1240  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
1241 
1242  if (instData.GLC)
1243  setFlag(GloballyCoherent);
1244 
1245  if (instData.SLC)
1246  setFlag(SystemCoherent);
1247  } // Inst_MUBUF
1248 
1250  {
1251  } // ~Inst_MUBUF
1252 
1253  void
1255  {
1256  // Currently there are three formats:
1257  // 0 src + 0 dst
1258  // 3 src + 1 dst
1259  // 4 src + 0 dst
1260  int opNum = 0;
1261 
1262  // Needed because can't take addr of bitfield;
1263  int reg = 0;
1264 
1265  if (numSrcRegOperands()) {
1266  if (numSrcRegOperands() == getNumOperands()) {
1267  reg = extData.VDATA;
1268  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1269  false, true, false);
1270  opNum++;
1271  }
1272 
1273  reg = extData.VADDR;
1274  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1275  false, true, false);
1276  opNum++;
1277 
1278  reg = extData.SRSRC;
1279  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1280  isScalarReg(reg), false, false);
1281  opNum++;
1282 
1283  reg = extData.SOFFSET;
1284  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1285  isScalarReg(reg), false, false);
1286  opNum++;
1287  }
1288 
1289  // extData.VDATA moves in the reg list depending on the instruction
1290  if (numDstRegOperands()) {
1291  reg = extData.VDATA;
1292  dstOps.emplace_back(reg, getOperandSize(opNum), false,
1293  false, true, false);
1294  }
1295 
1296  assert(srcOps.size() == numSrcRegOperands());
1297  assert(dstOps.size() == numDstRegOperands());
1298  }
1299 
1300  int
1302  {
1303  return 8;
1304  } // instSize
1305 
1306  void
1308  {
1309  // SRSRC is always in units of 4 SGPRs
1310  int srsrc_val = extData.SRSRC * 4;
1311  std::stringstream dis_stream;
1312  dis_stream << _opcode << " ";
1313  dis_stream << "v" << extData.VDATA << ", v" << extData.VADDR << ", ";
1314  dis_stream << "s[" << srsrc_val << ":"
1315  << srsrc_val + 3 << "], ";
1316  dis_stream << "s" << extData.SOFFSET;
1317 
1318  if (instData.OFFSET)
1319  dis_stream << ", offset:" << instData.OFFSET;
1320 
1321  disassembly = dis_stream.str();
1322  }
1323 
1324  // --- Inst_MTBUF base class methods ---
1325 
1326  Inst_MTBUF::Inst_MTBUF(InFmt_MTBUF *iFmt, const std::string &opcode)
1328  {
1329  // copy first instruction DWORD
1330  instData = iFmt[0];
1331  // copy second instruction DWORD
1332  extData = ((InFmt_MTBUF_1 *)iFmt)[1];
1333  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
1334 
1335  if (instData.GLC)
1336  setFlag(GloballyCoherent);
1337 
1338  if (extData.SLC)
1339  setFlag(SystemCoherent);
1340  } // Inst_MTBUF
1341 
1343  {
1344  } // ~Inst_MTBUF
1345 
1346  void
1348  {
1349  // Currently there are two formats:
1350  // 3 src + 1 dst
1351  // 4 src + 0 dst
1352  int opNum = 0;
1353 
1354  // Needed because can't take addr of bitfield
1355  int reg = 0;
1356 
1357  if (numSrcRegOperands() == getNumOperands()) {
1358  reg = extData.VDATA;
1359  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1360  false, true, false);
1361  opNum++;
1362  }
1363 
1364  reg = extData.VADDR;
1365  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1366  false, true, false);
1367  opNum++;
1368 
1369  reg = extData.SRSRC;
1370  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1371  isScalarReg(reg), false, false);
1372  opNum++;
1373 
1374  reg = extData.SOFFSET;
1375  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1376  isScalarReg(reg), false, false);
1377  opNum++;
1378 
1379  // extData.VDATA moves in the reg list depending on the instruction
1380  if (numDstRegOperands()) {
1381  reg = extData.VDATA;
1382  dstOps.emplace_back(reg, getOperandSize(opNum), false,
1383  false, true, false);
1384  }
1385 
1386  assert(srcOps.size() == numSrcRegOperands());
1387  assert(dstOps.size() == numDstRegOperands());
1388  }
1389 
1390  int
1392  {
1393  return 8;
1394  } // instSize
1395 
1396  // --- Inst_MIMG base class methods ---
1397 
1398  Inst_MIMG::Inst_MIMG(InFmt_MIMG *iFmt, const std::string &opcode)
1400  {
1401  // copy first instruction DWORD
1402  instData = iFmt[0];
1403  // copy second instruction DWORD
1404  extData = ((InFmt_MIMG_1 *)iFmt)[1];
1405  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
1406 
1407  if (instData.GLC)
1408  setFlag(GloballyCoherent);
1409 
1410  if (instData.SLC)
1411  setFlag(SystemCoherent);
1412  } // Inst_MIMG
1413 
1415  {
1416  } // ~Inst_MIMG
1417 
1418  void
1420  {
1421  // Three formats:
1422  // 1 dst + 2 src : s,s,d
1423  // 0 dst + 3 src : s,s,s
1424  // 1 dst + 3 src : s,s,s,d
1425  int opNum = 0;
1426 
1427  // Needed because can't take addr of bitfield
1428  int reg = 0;
1429 
1430  if (numSrcRegOperands() == getNumOperands()) {
1431  reg = extData.VDATA;
1432  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1433  false, true, false);
1434  opNum++;
1435  }
1436 
1437  reg = extData.VADDR;
1438  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1439  false, true, false);
1440  opNum++;
1441 
1442  reg = extData.SRSRC;
1443  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1444  isScalarReg(reg), false, false);
1445  opNum++;
1446 
1447  if (getNumOperands() == 4) {
1448  reg = extData.SSAMP;
1449  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1450  isScalarReg(reg), false, false);
1451  opNum++;
1452  }
1453 
1454  // extData.VDATA moves in the reg list depending on the instruction
1455  if (numDstRegOperands()) {
1456  reg = extData.VDATA;
1457  dstOps.emplace_back(reg, getOperandSize(opNum), false,
1458  false, true, false);
1459  }
1460 
1461  assert(srcOps.size() == numSrcRegOperands());
1462  assert(dstOps.size() == numDstRegOperands());
1463  }
1464 
1465  int
1467  {
1468  return 8;
1469  } // instSize
1470 
1471  // --- Inst_EXP base class methods ---
1472 
1473  Inst_EXP::Inst_EXP(InFmt_EXP *iFmt, const std::string &opcode)
1475  {
1476  // copy first instruction DWORD
1477  instData = iFmt[0];
1478  // copy second instruction DWORD
1479  extData = ((InFmt_EXP_1 *)iFmt)[1];
1480  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
1481  } // Inst_EXP
1482 
1484  {
1485  } // ~Inst_EXP
1486 
1487  void
1489  {
1490  // Only 1 instruction, 1 format: 1 dst + 4 src
1491  int opNum = 0;
1492 
1493  // Avoids taking addr of bitfield
1494  unsigned int srcs[4] = {extData.VSRC0, extData.VSRC1,
1496 
1497  for (opNum = 0; opNum < 4; opNum++) {
1498  srcOps.emplace_back(srcs[opNum], getOperandSize(opNum), true,
1499  false, true, false);
1500  }
1501 
1502  //TODO: Add the dst operand, don't know what it is right now
1503  }
1504 
1505  int
1507  {
1508  return 8;
1509  } // instSize
1510 
1511  // --- Inst_FLAT base class methods ---
1512 
1513  Inst_FLAT::Inst_FLAT(InFmt_FLAT *iFmt, const std::string &opcode)
1515  {
1516  setFlag(Flat);
1517  // copy first instruction DWORD
1518  instData = iFmt[0];
1519  // copy second instruction DWORD
1520  extData = ((InFmt_FLAT_1 *)iFmt)[1];
1521  _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
1522 
1523  if (instData.GLC)
1524  setFlag(GloballyCoherent);
1525 
1526  if (instData.SLC)
1527  setFlag(SystemCoherent);
1528  } // Inst_FLAT
1529 
1531  {
1532  } // ~Inst_FLAT
1533 
1534  void
1536  {
1537  //3 formats:
1538  // 1 dst + 1 src (load)
1539  // 0 dst + 2 src (store)
1540  // 1 dst + 2 src (atomic)
1541  int opNum = 0;
1542 
1543  // Needed because can't take addr of bitfield
1544  int reg = 0;
1545 
1546  if (getNumOperands() > 2)
1547  assert(isAtomic());
1548 
1549  reg = extData.ADDR;
1550  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1551  false, true, false);
1552  opNum++;
1553 
1554  if (numSrcRegOperands() == 2) {
1555  reg = extData.DATA;
1556  srcOps.emplace_back(reg, getOperandSize(opNum), true,
1557  false, true, false);
1558  opNum++;
1559  }
1560 
1561  if (numDstRegOperands()) {
1562  reg = extData.VDST;
1563  dstOps.emplace_back(reg, getOperandSize(opNum), false,
1564  false, true, false);
1565  }
1566 
1567  assert(srcOps.size() == numSrcRegOperands());
1568  assert(dstOps.size() == numDstRegOperands());
1569  }
1570 
1571  int
1573  {
1574  return 8;
1575  } // instSize
1576 
1577  void
1579  {
1580  std::stringstream dis_stream;
1581  dis_stream << _opcode << " ";
1582 
1583  if (isLoad())
1584  dis_stream << "v" << extData.VDST << ", ";
1585 
1586  dis_stream << "v[" << extData.ADDR << ":" << extData.ADDR + 1 << "]";
1587 
1588  if (isStore())
1589  dis_stream << ", v" << extData.DATA;
1590 
1591  disassembly = dis_stream.str();
1592  }
1593 } // namespace Gcn3ISA
1594 } // namespace gem5
gem5::Gcn3ISA::InFmt_SOP1::SDST
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Definition: gpu_decoder.hh:1510
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Definition: statistics.hh:1927
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Definition: gpu_registers.hh:126
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Definition: op_encodings.hh:919
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Definition: gpu_decoder.hh:1575
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Definition: op_encodings.cc:1170
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Definition: op_encodings.cc:685
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Definition: gpu_decoder.hh:1567
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Definition: op_encodings.cc:358
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Definition: op_encodings.cc:93
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Definition: op_encodings.hh:153
gem5::Gcn3ISA::Inst_VOP1::hasSecondDword
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Definition: op_encodings.cc:779
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Definition: registers.cc:218
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Definition: gpu_decoder.hh:1482
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Definition: op_encodings.cc:247
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Definition: gpu_types.hh:63
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Definition: op_encodings.cc:1530
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Definition: gpu_decoder.hh:1539
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Definition: gpu_decoder.hh:1516
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Definition: op_encodings.hh:133
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Definition: op_encodings.hh:783
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Definition: op_encodings.cc:152
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Definition: gpu_decoder.hh:1375
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Definition: registers.cc:42
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Definition: op_encodings.cc:893
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Definition: registers.cc:231
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Definition: op_encodings.cc:615
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Definition: op_encodings.cc:798
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Definition: op_encodings.cc:283
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Definition: op_encodings.hh:318
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Definition: op_encodings.cc:654
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Definition: types.hh:144
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Definition: op_encodings.cc:1578
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Definition: op_encodings.cc:1513
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Definition: gpu_decoder.hh:1586
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Definition: gpu_decoder.hh:1480
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Definition: op_encodings.hh:781
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Definition: op_encodings.cc:1473
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Definition: op_encodings.cc:87
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Definition: gpu_decoder.hh:1388
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Definition: op_encodings.hh:275
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Definition: gpu_decoder.hh:1495
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Definition: op_encodings.hh:134
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Definition: op_encodings.hh:383
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Definition: op_encodings.cc:868
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Definition: gpu_decoder.hh:1463
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Definition: op_encodings.hh:175
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Definition: op_encodings.cc:844
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Definition: gpu_decoder.hh:1514
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Definition: op_encodings.cc:63
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Definition: op_encodings.hh:351
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Definition: op_encodings.cc:396
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Definition: gpu_static_inst.hh:149
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Definition: gpu_static_inst.hh:134
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Definition: op_encodings.cc:913
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Definition: gpu_decoder.hh:1542
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Definition: gpu_decoder.hh:1556
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Definition: gpu_decoder.hh:1496
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Definition: op_encodings.hh:746
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Definition: gpu_decoder.hh:1546
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Definition: gpu_decoder.hh:1526
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@ REG_VCC_LO
Definition: gpu_registers.hh:58
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Definition: types.hh:92
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Definition: op_encodings.cc:1108
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Definition: op_encodings.cc:203
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Definition: op_encodings.hh:296
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Definition: gpu_decoder.hh:1418
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Definition: op_encodings.hh:156
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Definition: op_encodings.hh:385
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Definition: gpu_decoder.hh:1587
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Definition: gpu_static_inst.hh:299
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Definition: gpu_decoder.hh:1672
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Definition: op_encodings.cc:318
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Definition: gpu_decoder.hh:1448
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Definition: gpu_registers.hh:127
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Definition: op_encodings.cc:773
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Definition: op_encodings.cc:987
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Definition: op_encodings.cc:497
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Definition: op_encodings.cc:268
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Definition: gpu_decoder.hh:1394
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Definition: op_encodings.cc:420
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Definition: op_encodings.hh:254
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Definition: gpu_decoder.hh:1573
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Definition: gpu_decoder.hh:1535
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Definition: gpu_decoder.hh:1592
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Definition: gpu_decoder.hh:1506
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Definition: op_encodings.cc:481
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Definition: gpu_decoder.hh:1457
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Definition: op_encodings.cc:323
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Definition: gpu_registers.hh:132
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Definition: gpu_decoder.hh:1429
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Definition: gpu_decoder.hh:1466
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Definition: op_encodings.cc:554
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Definition: op_encodings.hh:319
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Definition: gpu_decoder.hh:1443
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Definition: op_encodings.cc:1062
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Definition: op_encodings.cc:391
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
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Definition: gpu_decoder.hh:1371
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Definition: gpu_decoder.hh:1372
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Definition: op_encodings.hh:524
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Definition: op_encodings.hh:294
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Definition: op_encodings.hh:767
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Definition: op_encodings.cc:660
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Definition: gpu_decoder.hh:1423
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Definition: gpu_decoder.hh:1492
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Definition: gpu_decoder.hh:1490
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int instSize() const override
Definition: op_encodings.cc:548
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Definition: gpu_decoder.hh:1357
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Definition: gpu_decoder.hh:1583
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unsigned int OFFSET
Definition: gpu_decoder.hh:1503
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virtual int numDstRegOperands()=0
gem5::Gcn3ISA::Inst_SOPK::~Inst_SOPK
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Definition: op_encodings.cc:147
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Definition: op_encodings.cc:936
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Definition: gpu_static_inst.hh:245
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Definition: gpu_decoder.hh:1468
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Definition: gpu_static_inst.hh:49
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Definition: op_encodings.cc:1307
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Definition: gpu_decoder.hh:1493

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