|
gem5
v22.1.0.0
|
#include "arch/amdgpu/gcn3/gpu_registers.hh"Go to the source code of this file.
Namespaces | |
| gem5 | |
| Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223. | |
| gem5::Gcn3ISA | |
| classes that represnt vector/scalar operands in GCN3 ISA. | |
Functions | |
| std::string | gem5::Gcn3ISA::opSelectorToRegSym (int opIdx, int numRegs=0) |
| int | gem5::Gcn3ISA::opSelectorToRegIdx (int opIdx, int numScalarRegs) |
| bool | gem5::Gcn3ISA::isPosConstVal (int opIdx) |
| bool | gem5::Gcn3ISA::isNegConstVal (int opIdx) |
| bool | gem5::Gcn3ISA::isConstVal (int opIdx) |
| bool | gem5::Gcn3ISA::isLiteral (int opIdx) |
| bool | gem5::Gcn3ISA::isExecMask (int opIdx) |
| bool | gem5::Gcn3ISA::isVccReg (int opIdx) |
| bool | gem5::Gcn3ISA::isFlatScratchReg (int opIdx) |
| bool | gem5::Gcn3ISA::isScalarReg (int opIdx) |
| bool | gem5::Gcn3ISA::isVectorReg (int opIdx) |