gem5  v22.1.0.0
registers.cc
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31 
33 
34 namespace gem5
35 {
36 
37 namespace Gcn3ISA
38 {
39  std::string
40  opSelectorToRegSym(int idx, int numRegs)
41  {
42  std::string reg_sym;
43 
44  // we have an SGPR
45  if (idx <= REG_SGPR_MAX) {
46  if (numRegs > 1)
47  reg_sym = "s[" + std::to_string(idx) + ":" +
48  std::to_string(idx + numRegs - 1) + "]";
49  else
50  reg_sym = "s" + std::to_string(idx);
51  return reg_sym;
52  } else if (idx >= REG_VGPR_MIN && idx <= REG_VGPR_MAX) {
53  if (numRegs > 1)
54  reg_sym = "v[" + std::to_string(idx - REG_VGPR_MIN) + ":" +
55  std::to_string(idx - REG_VGPR_MIN + numRegs - 1) + "]";
56  else
57  reg_sym = "v" + std::to_string(idx - REG_VGPR_MIN);
58  return reg_sym;
59  } else if (idx >= REG_INT_CONST_POS_MIN &&
60  idx <= REG_INT_CONST_POS_MAX) {
61  reg_sym = std::to_string(idx - REG_INT_CONST_POS_MIN + 1);
62  return reg_sym;
63  } else if (idx >= REG_INT_CONST_NEG_MIN &&
64  idx <= REG_INT_CONST_NEG_MAX) {
65  int inline_val = -1 - (idx - REG_INT_CONST_NEG_MIN);
66  reg_sym = std::to_string(inline_val);
67  return reg_sym;
68  }
69 
70  switch (idx) {
72  reg_sym = "flat_scratch_lo";
73  break;
75  reg_sym = "flat_scratch_hi";
76  break;
77  case REG_VCC_LO:
78  reg_sym = "vcc_lo";
79  break;
80  case REG_VCC_HI:
81  reg_sym = "vcc_hi";
82  break;
83  case REG_M0:
84  reg_sym = "m0";
85  break;
86  case REG_EXEC_LO:
87  reg_sym = "exec";
88  break;
89  case REG_ZERO:
90  reg_sym = "0";
91  break;
92  case REG_POS_HALF:
93  reg_sym = "0.5";
94  break;
95  case REG_NEG_HALF:
96  reg_sym = "-0.5";
97  break;
98  case REG_POS_ONE:
99  reg_sym = "1";
100  break;
101  case REG_NEG_ONE:
102  reg_sym = "-1";
103  break;
104  case REG_POS_TWO:
105  reg_sym = "2";
106  break;
107  case REG_NEG_TWO:
108  reg_sym = "-2";
109  break;
110  case REG_POS_FOUR:
111  reg_sym = "4";
112  break;
113  case REG_NEG_FOUR:
114  reg_sym = "-4";
115  break;
116  default:
117  fatal("GCN3 ISA instruction has unknown register index %u\n", idx);
118  break;
119  }
120 
121  return reg_sym;
122  }
123 
124  int
125  opSelectorToRegIdx(int idx, int numScalarRegs)
126  {
127  int regIdx = -1;
128 
129  if (idx <= REG_SGPR_MAX) {
130  regIdx = idx;
131  } else if (idx >= REG_VGPR_MIN && idx <= REG_VGPR_MAX) {
132  regIdx = idx - REG_VGPR_MIN;
133  } else if (idx == REG_VCC_LO) {
145  regIdx = numScalarRegs - 2;
146  } else if (idx == REG_VCC_HI) {
147  regIdx = numScalarRegs - 1;
148  } else if (idx == REG_FLAT_SCRATCH_LO) {
161  regIdx = numScalarRegs - 4;
162  } else if (idx == REG_FLAT_SCRATCH_HI) {
163  regIdx = numScalarRegs - 3;
164  }
165 
166  return regIdx;
167  }
168 
169  bool
170  isPosConstVal(int opIdx)
171  {
172  bool is_pos_const_val = (opIdx >= REG_INT_CONST_POS_MIN
173  && opIdx <= REG_INT_CONST_POS_MAX);
174 
175  return is_pos_const_val;
176  }
177 
178  bool
179  isNegConstVal(int opIdx)
180  {
181  bool is_neg_const_val = (opIdx >= REG_INT_CONST_NEG_MIN
182  && opIdx <= REG_INT_CONST_NEG_MAX);
183 
184  return is_neg_const_val;
185  }
186 
187  bool
188  isConstVal(int opIdx)
189  {
190  bool is_const_val = isPosConstVal(opIdx) || isNegConstVal(opIdx);
191  return is_const_val;
192  }
193 
194  bool
195  isLiteral(int opIdx)
196  {
197  return opIdx == REG_SRC_LITERAL;
198  }
199 
200  bool
201  isExecMask(int opIdx)
202  {
203  return opIdx == REG_EXEC_LO || opIdx == REG_EXEC_HI;
204  }
205 
206  bool
207  isVccReg(int opIdx)
208  {
209  return opIdx == REG_VCC_LO || opIdx == REG_VCC_HI;
210  }
211 
212  bool
213  isFlatScratchReg(int opIdx)
214  {
215  return opIdx == REG_FLAT_SCRATCH_LO || opIdx == REG_FLAT_SCRATCH_HI;
216  }
217 
218  bool
219  isScalarReg(int opIdx)
220  {
221  // FLAT_SCRATCH and VCC are stored in an SGPR pair
222  if (opIdx <= REG_SGPR_MAX || opIdx == REG_FLAT_SCRATCH_LO ||
223  opIdx == REG_FLAT_SCRATCH_HI || opIdx == REG_VCC_LO ||
224  opIdx == REG_VCC_HI) {
225  return true;
226  }
227 
228  return false;
229  }
230 
231  bool
232  isVectorReg(int opIdx)
233  {
234  if (opIdx >= REG_VGPR_MIN && opIdx <= REG_VGPR_MAX)
235  return true;
236 
237  return false;
238  }
239 
240 } // namespace Gcn3ISA
241 } // namespace gem5
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
bool isNegConstVal(int opIdx)
Definition: registers.cc:179
bool isFlatScratchReg(int opIdx)
Definition: registers.cc:213
int opSelectorToRegIdx(int opIdx, int numScalarRegs)
Definition: registers.cc:125
bool isExecMask(int opIdx)
Definition: registers.cc:201
std::string opSelectorToRegSym(int opIdx, int numRegs=0)
Definition: registers.cc:40
bool isScalarReg(int opIdx)
Definition: registers.cc:219
bool isVectorReg(int opIdx)
Definition: registers.cc:232
bool isPosConstVal(int opIdx)
Definition: registers.cc:170
bool isConstVal(int opIdx)
Definition: registers.cc:188
bool isVccReg(int opIdx)
Definition: registers.cc:207
bool isLiteral(int opIdx)
Definition: registers.cc:195
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
const std::string to_string(sc_enc enc)
Definition: sc_fxdefs.cc:60

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