gem5  v22.0.0.1
registers.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015-2021 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright notice,
12  * this list of conditions and the following disclaimer in the documentation
13  * and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  * contributors may be used to endorse or promote products derived from this
17  * software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
33 
34 namespace gem5
35 {
36 
37 namespace Gcn3ISA
38 {
39  std::string
40  opSelectorToRegSym(int idx, int numRegs)
41  {
42  std::string reg_sym;
43 
44  // we have an SGPR
45  if (idx <= REG_SGPR_MAX) {
46  if (numRegs > 1)
47  reg_sym = "s[" + std::to_string(idx) + ":" +
48  std::to_string(idx + numRegs - 1) + "]";
49  else
50  reg_sym = "s" + std::to_string(idx);
51  return reg_sym;
52  } else if (idx >= REG_VGPR_MIN && idx <= REG_VGPR_MAX) {
53  if (numRegs > 1)
54  reg_sym = "v[" + std::to_string(idx - REG_VGPR_MIN) + ":" +
55  std::to_string(idx - REG_VGPR_MIN + numRegs - 1) + "]";
56  else
57  reg_sym = "v" + std::to_string(idx - REG_VGPR_MIN);
58  return reg_sym;
59  } else if (idx >= REG_INT_CONST_POS_MIN &&
60  idx <= REG_INT_CONST_POS_MAX) {
61  reg_sym = std::to_string(idx - REG_INT_CONST_POS_MIN + 1);
62  return reg_sym;
63  } else if (idx >= REG_INT_CONST_NEG_MIN &&
64  idx <= REG_INT_CONST_NEG_MAX) {
65  int inline_val = -1 - (idx - REG_INT_CONST_NEG_MIN);
66  reg_sym = std::to_string(inline_val);
67  return reg_sym;
68  }
69 
70  switch (idx) {
72  reg_sym = "flat_scratch_lo";
73  break;
75  reg_sym = "flat_scratch_hi";
76  break;
77  case REG_VCC_LO:
78  reg_sym = "vcc";
79  break;
80  case REG_M0:
81  reg_sym = "m0";
82  break;
83  case REG_EXEC_LO:
84  reg_sym = "exec";
85  break;
86  case REG_ZERO:
87  reg_sym = "0";
88  break;
89  case REG_POS_HALF:
90  reg_sym = "0.5";
91  break;
92  case REG_NEG_HALF:
93  reg_sym = "-0.5";
94  break;
95  case REG_POS_ONE:
96  reg_sym = "1";
97  break;
98  case REG_NEG_ONE:
99  reg_sym = "-1";
100  break;
101  case REG_POS_TWO:
102  reg_sym = "2";
103  break;
104  case REG_NEG_TWO:
105  reg_sym = "-2";
106  break;
107  case REG_POS_FOUR:
108  reg_sym = "4";
109  break;
110  case REG_NEG_FOUR:
111  reg_sym = "-4";
112  break;
113  default:
114  fatal("GCN3 ISA instruction has unknown register index %u\n", idx);
115  break;
116  }
117 
118  return reg_sym;
119  }
120 
121  int
122  opSelectorToRegIdx(int idx, int numScalarRegs)
123  {
124  int regIdx = -1;
125 
126  if (idx <= REG_SGPR_MAX) {
127  regIdx = idx;
128  } else if (idx >= REG_VGPR_MIN && idx <= REG_VGPR_MAX) {
129  regIdx = idx - REG_VGPR_MIN;
130  } else if (idx == REG_VCC_LO) {
142  regIdx = numScalarRegs - 2;
143  } else if (idx == REG_VCC_HI) {
144  regIdx = numScalarRegs - 1;
145  } else if (idx == REG_FLAT_SCRATCH_LO) {
158  regIdx = numScalarRegs - 4;
159  } else if (idx == REG_FLAT_SCRATCH_HI) {
160  regIdx = numScalarRegs - 3;
161  }
162 
163  return regIdx;
164  }
165 
166  bool
167  isPosConstVal(int opIdx)
168  {
169  bool is_pos_const_val = (opIdx >= REG_INT_CONST_POS_MIN
170  && opIdx <= REG_INT_CONST_POS_MAX);
171 
172  return is_pos_const_val;
173  }
174 
175  bool
176  isNegConstVal(int opIdx)
177  {
178  bool is_neg_const_val = (opIdx >= REG_INT_CONST_NEG_MIN
179  && opIdx <= REG_INT_CONST_NEG_MAX);
180 
181  return is_neg_const_val;
182  }
183 
184  bool
185  isConstVal(int opIdx)
186  {
187  bool is_const_val = isPosConstVal(opIdx) || isNegConstVal(opIdx);
188  return is_const_val;
189  }
190 
191  bool
192  isLiteral(int opIdx)
193  {
194  return opIdx == REG_SRC_LITERAL;
195  }
196 
197  bool
198  isExecMask(int opIdx)
199  {
200  return opIdx == REG_EXEC_LO || opIdx == REG_EXEC_HI;
201  }
202 
203  bool
204  isVccReg(int opIdx)
205  {
206  return opIdx == REG_VCC_LO || opIdx == REG_VCC_HI;
207  }
208 
209  bool
210  isFlatScratchReg(int opIdx)
211  {
212  return opIdx == REG_FLAT_SCRATCH_LO || opIdx == REG_FLAT_SCRATCH_HI;
213  }
214 
215  bool
216  isScalarReg(int opIdx)
217  {
218  // FLAT_SCRATCH and VCC are stored in an SGPR pair
219  if (opIdx <= REG_SGPR_MAX || opIdx == REG_FLAT_SCRATCH_LO ||
220  opIdx == REG_FLAT_SCRATCH_HI || opIdx == REG_VCC_LO ||
221  opIdx == REG_VCC_HI) {
222  return true;
223  }
224 
225  return false;
226  }
227 
228  bool
229  isVectorReg(int opIdx)
230  {
231  if (opIdx >= REG_VGPR_MIN && opIdx <= REG_VGPR_MAX)
232  return true;
233 
234  return false;
235  }
236 
237 } // namespace Gcn3ISA
238 } // namespace gem5
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::Gcn3ISA::REG_VGPR_MIN
@ REG_VGPR_MIN
Definition: gpu_registers.hh:131
gem5::Gcn3ISA::REG_NEG_TWO
@ REG_NEG_TWO
Definition: gpu_registers.hh:119
gem5::Gcn3ISA::REG_EXEC_LO
@ REG_EXEC_LO
Definition: gpu_registers.hh:76
gem5::Gcn3ISA::REG_INT_CONST_POS_MIN
@ REG_INT_CONST_POS_MIN
Definition: gpu_registers.hh:79
gem5::Gcn3ISA::isNegConstVal
bool isNegConstVal(int opIdx)
Definition: registers.cc:176
gem5::Gcn3ISA::isScalarReg
bool isScalarReg(int opIdx)
Definition: registers.cc:216
gem5::Gcn3ISA::isPosConstVal
bool isPosConstVal(int opIdx)
Definition: registers.cc:167
gem5::Gcn3ISA::opSelectorToRegSym
std::string opSelectorToRegSym(int opIdx, int numRegs=0)
Definition: registers.cc:40
gem5::Gcn3ISA::REG_POS_TWO
@ REG_POS_TWO
Definition: gpu_registers.hh:118
gpu_registers.hh
gem5::Gcn3ISA::REG_EXEC_HI
@ REG_EXEC_HI
Definition: gpu_registers.hh:77
sc_dt::to_string
const std::string to_string(sc_enc enc)
Definition: sc_fxdefs.cc:91
gem5::Gcn3ISA::REG_SRC_LITERAL
@ REG_SRC_LITERAL
Definition: gpu_registers.hh:130
gem5::Gcn3ISA::REG_NEG_FOUR
@ REG_NEG_FOUR
Definition: gpu_registers.hh:121
gem5::Gcn3ISA::REG_NEG_ONE
@ REG_NEG_ONE
Definition: gpu_registers.hh:117
gem5::Gcn3ISA::isVccReg
bool isVccReg(int opIdx)
Definition: registers.cc:204
gem5::Gcn3ISA::REG_VCC_LO
@ REG_VCC_LO
Definition: gpu_registers.hh:56
gem5::Gcn3ISA::isExecMask
bool isExecMask(int opIdx)
Definition: registers.cc:198
gem5::Gcn3ISA::REG_INT_CONST_NEG_MIN
@ REG_INT_CONST_NEG_MIN
Definition: gpu_registers.hh:81
gem5::Gcn3ISA::REG_SGPR_MAX
@ REG_SGPR_MAX
Definition: gpu_registers.hh:51
gem5::Gcn3ISA::isVectorReg
bool isVectorReg(int opIdx)
Definition: registers.cc:229
gem5::Gcn3ISA::isLiteral
bool isLiteral(int opIdx)
Definition: registers.cc:192
gem5::Gcn3ISA::REG_FLAT_SCRATCH_LO
@ REG_FLAT_SCRATCH_LO
Definition: gpu_registers.hh:52
gem5::Gcn3ISA::opSelectorToRegIdx
int opSelectorToRegIdx(int opIdx, int numScalarRegs)
Definition: registers.cc:122
gem5::Gcn3ISA::REG_VGPR_MAX
@ REG_VGPR_MAX
Definition: gpu_registers.hh:132
gem5::Gcn3ISA::REG_FLAT_SCRATCH_HI
@ REG_FLAT_SCRATCH_HI
Definition: gpu_registers.hh:53
gem5::Gcn3ISA::REG_INT_CONST_POS_MAX
@ REG_INT_CONST_POS_MAX
Definition: gpu_registers.hh:80
gem5::Gcn3ISA::REG_NEG_HALF
@ REG_NEG_HALF
Definition: gpu_registers.hh:115
gem5::Gcn3ISA::REG_POS_HALF
@ REG_POS_HALF
Definition: gpu_registers.hh:114
gem5::Gcn3ISA::REG_POS_FOUR
@ REG_POS_FOUR
Definition: gpu_registers.hh:120
gem5::Gcn3ISA::REG_POS_ONE
@ REG_POS_ONE
Definition: gpu_registers.hh:116
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::Gcn3ISA::REG_INT_CONST_NEG_MAX
@ REG_INT_CONST_NEG_MAX
Definition: gpu_registers.hh:82
gem5::Gcn3ISA::REG_ZERO
@ REG_ZERO
Definition: gpu_registers.hh:78
gem5::Gcn3ISA::REG_VCC_HI
@ REG_VCC_HI
Definition: gpu_registers.hh:57
gem5::Gcn3ISA::REG_M0
@ REG_M0
Definition: gpu_registers.hh:74
gem5::Gcn3ISA::isConstVal
bool isConstVal(int opIdx)
Definition: registers.cc:185
gem5::Gcn3ISA::isFlatScratchReg
bool isFlatScratchReg(int opIdx)
Definition: registers.cc:210

Generated on Sat Jun 18 2022 08:12:12 for gem5 by doxygen 1.8.17