gem5  v21.1.0.2
gpu_tlb.hh
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33 
34 #ifndef __GPU_TLB_HH__
35 #define __GPU_TLB_HH__
36 
37 #include <fstream>
38 #include <list>
39 #include <queue>
40 #include <string>
41 #include <vector>
42 
43 #include "arch/generic/tlb.hh"
44 #include "arch/x86/pagetable.hh"
46 #include "arch/x86/regs/segment.hh"
47 #include "base/callback.hh"
48 #include "base/logging.hh"
49 #include "base/statistics.hh"
50 #include "base/stats/group.hh"
52 #include "mem/port.hh"
53 #include "mem/request.hh"
54 #include "params/X86GPUTLB.hh"
55 #include "sim/clocked_object.hh"
56 #include "sim/sim_object.hh"
57 
58 namespace gem5
59 {
60 
61 class BaseTLB;
62 class Packet;
63 class ThreadContext;
64 
65 namespace X86ISA
66 {
67  class GpuTLB : public ClockedObject
68  {
69  protected:
70  friend class Walker;
71 
73 
74  uint32_t configAddress;
75 
76  public:
77  typedef X86GPUTLBParams Params;
78  GpuTLB(const Params &p);
79  ~GpuTLB();
80 
81  typedef enum BaseMMU::Mode Mode;
82 
84  {
85  public:
86  virtual ~Translation() { }
87 
92  virtual void markDelayed() = 0;
93 
99  virtual void finish(Fault fault, const RequestPtr &req,
100  ThreadContext *tc, Mode mode) = 0;
101  };
102 
103  void dumpAll();
104  TlbEntry *lookup(Addr va, bool update_lru=true);
105  void setConfigAddress(uint32_t addr);
106 
107  protected:
108  EntryList::iterator lookupIt(Addr va, bool update_lru=true);
110 
111  public:
112  Walker *getWalker();
113  void invalidateAll();
114  void invalidateNonGlobal();
115  void demapPage(Addr va, uint64_t asn);
116 
117  protected:
118  int size;
119  int assoc;
120  int numSets;
121 
125  bool FA;
127 
133 
138 
144 
146 
147  /*
148  * It's a per-set list. As long as we have not reached
149  * the full capacity of the given set, grab an entry from
150  * the freeList.
151  */
153 
162 
163  Fault translateInt(bool read, const RequestPtr &req,
164  ThreadContext *tc);
165 
166  Fault translate(const RequestPtr &req, ThreadContext *tc,
167  Translation *translation, Mode mode, bool &delayedResponse,
168  bool timing, int &latency);
169 
170  public:
171  // latencies for a TLB hit, miss and page fault
175 
176  void updatePageFootprint(Addr virt_page_addr);
177  void printAccessPattern();
178 
179 
181  Mode mode, int &latency);
182 
183  void translateTiming(const RequestPtr &req, ThreadContext *tc,
184  Translation *translation, Mode mode,
185  int &latency);
186 
189 
190  TlbEntry *insert(Addr vpn, TlbEntry &entry);
191 
192  // Checkpointing
193  virtual void serialize(CheckpointOut& cp) const override;
194  virtual void unserialize(CheckpointIn& cp) override;
195  void issueTranslation();
197  bool tlbLookup(const RequestPtr &req,
198  ThreadContext *tc, bool update_stats);
199 
201  PacketPtr pkt);
202 
204 
206  TlbEntry *tlb_entry, Mode mode);
207 
208  void updatePhysAddresses(Addr virt_page_addr, TlbEntry *tlb_entry,
209  Addr phys_page_addr);
210 
211  void issueTLBLookup(PacketPtr pkt);
212 
213  // CpuSidePort is the TLB Port closer to the CPU/CU side
214  class CpuSidePort : public ResponsePort
215  {
216  public:
217  CpuSidePort(const std::string &_name, GpuTLB * gpu_TLB,
218  PortID _index)
219  : ResponsePort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { }
220 
221  protected:
223  int index;
224 
225  virtual bool recvTimingReq(PacketPtr pkt);
226  virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
227  virtual void recvFunctional(PacketPtr pkt);
228  virtual void recvRangeChange() { }
229  virtual void recvReqRetry();
230  virtual void recvRespRetry() { panic("recvRespRetry called"); }
231  virtual AddrRangeList getAddrRanges() const;
232  };
233 
241  class MemSidePort : public RequestPort
242  {
243  public:
244  MemSidePort(const std::string &_name, GpuTLB * gpu_TLB,
245  PortID _index)
246  : RequestPort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { }
247 
249 
250  protected:
252  int index;
253 
254  virtual bool recvTimingResp(PacketPtr pkt);
255  virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
256  virtual void recvFunctional(PacketPtr pkt) { }
257  virtual void recvRangeChange() { }
258  virtual void recvReqRetry();
259  };
260 
261  // TLB ports on the cpu Side
263  // TLB ports on the memory side
265 
266  Port &getPort(const std::string &if_name,
267  PortID idx=InvalidPortID) override;
268 
286  {
287  // TLB mode, read or write
289  // Thread context associated with this req
291 
292  /*
293  * TLB entry to be populated and passed back and filled in
294  * previous TLBs. Equivalent to the data cache concept of
295  * "data return."
296  */
298  // Is this a TLB prefetch request?
300  // When was the req for this translation issued
301  uint64_t issueTime;
302  // Remember where this came from
304 
305  // keep track of #uncoalesced reqs per packet per TLB level;
306  // reqCnt per level >= reqCnt higher level
308  // TLB level this packet hit in; 0 if it hit in the page table
309  int hitLevel;
311 
313  bool is_prefetch=false,
314  Packet::SenderState *_saved=nullptr)
315  : tlbMode(tlb_mode), tc(_tc), tlbEntry(nullptr),
316  isPrefetch(is_prefetch), issueTime(0),
317  hitLevel(0),saved(_saved) { }
318  };
319 
320  // maximum number of permitted coalesced requests per cycle
322 
323  // Current number of outstandings coalesced requests.
324  // Should be <= maxCoalescedReqs
326 
334  void translationReturn(Addr virtPageAddr, tlbOutcome outcome,
335  PacketPtr pkt);
336 
337  class TLBEvent : public Event
338  {
339  private:
347 
348  public:
349  TLBEvent(GpuTLB *_tlb, Addr _addr, tlbOutcome outcome,
350  PacketPtr _pkt);
351 
352  void process();
353  const char *description() const;
354 
355  // updateOutcome updates the tlbOutcome of a TLBEvent
356  void updateOutcome(tlbOutcome _outcome);
358  };
359 
360  std::unordered_map<Addr, TLBEvent*> translationReturnEvent;
361 
362  // this FIFO queue keeps track of the virt. page addresses
363  // that are pending cleanup
364  std::queue<Addr> cleanupQueue;
365 
366  // the cleanupEvent is scheduled after a TLBEvent triggers in order to
367  // free memory and do the required clean-up
368  void cleanup();
369 
371 
377  struct AccessInfo
378  {
379  unsigned int lastTimeAccessed; // last access to this page
380  unsigned int accessesPerPage;
381  // need to divide it by accessesPerPage at the end
382  unsigned int totalReuseDistance;
383 
393  unsigned int sumDistance;
394  unsigned int meanDistance;
395  };
396 
397  typedef std::unordered_map<Addr, AccessInfo> AccessPatternTable;
399 
400  // Called at the end of simulation to dump page access stats.
401  void exitCallback();
402 
404 
405  protected:
407  {
409 
410  // local_stats are as seen from the TLB
411  // without taking into account coalescing
416 
417  // global_stats are as seen from the
418  // CU's perspective taking into account
419  // all coalesced requests.
424 
425  // from the CU perspective (global)
427  // from the CU perspective (global)
430  // from the perspective of this TLB
432  // from the perspective of this TLB
434  // I take the avg. per page and then
435  // the avg. over all pages.
437  } stats;
438  };
439 }
440 
441 } // namespace gem5
442 
443 #endif // __GPU_TLB_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::X86ISA::GpuTLB::issueTranslation
void issueTranslation()
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
pagetable.hh
gem5::X86ISA::GpuTLB::configAddress
uint32_t configAddress
Definition: gpu_tlb.hh:74
gem5::X86ISA::GpuTLB::GpuTLBStats::numUniquePages
statistics::Scalar numUniquePages
Definition: gpu_tlb.hh:429
gem5::X86ISA::GpuTLB::printAccessPattern
void printAccessPattern()
gem5::X86ISA::GpuTLB::updatePhysAddresses
void updatePhysAddresses(Addr virt_page_addr, TlbEntry *tlb_entry, Addr phys_page_addr)
gem5::X86ISA::GpuTLB::MemSidePort::index
int index
Definition: gpu_tlb.hh:252
gem5::X86ISA::GpuTLB::GpuTLBStats::GpuTLBStats
GpuTLBStats(statistics::Group *parent)
Definition: gpu_tlb.cc:1435
gem5::X86ISA::GpuTLB::GpuTLBStats::accessCycles
statistics::Scalar accessCycles
Definition: gpu_tlb.hh:426
gem5::X86ISA::GpuTLB::CpuSidePort::CpuSidePort
CpuSidePort(const std::string &_name, GpuTLB *gpu_TLB, PortID _index)
Definition: gpu_tlb.hh:217
gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Receive a functional request packet from the peer.
Definition: gpu_tlb.cc:1123
gem5::X86ISA::GpuTLB::translationReturn
void translationReturn(Addr virtPageAddr, tlbOutcome outcome, PacketPtr pkt)
A TLBEvent is scheduled after the TLB lookup and helps us take the appropriate actions: (e....
Definition: gpu_tlb.cc:884
gem5::X86ISA::GpuTLB::stats
gem5::X86ISA::GpuTLB::GpuTLBStats stats
gem5::X86ISA::GpuTLB::memSidePort
std::vector< MemSidePort * > memSidePort
Definition: gpu_tlb.hh:264
gem5::X86ISA::GpuTLB::GpuTLBStats::avgReuseDistance
statistics::Scalar avgReuseDistance
Definition: gpu_tlb.hh:436
gem5::X86ISA::GpuTLB::size
int size
Definition: gpu_tlb.hh:118
gem5::X86ISA::GpuTLB::AccessInfo::localTLBAccesses
std::vector< unsigned int > localTLBAccesses
The field below will help us compute the access distance, that is the number of (coalesced) TLB acces...
Definition: gpu_tlb.hh:392
gem5::X86ISA::GpuTLB::TranslationState::tc
ThreadContext * tc
Definition: gpu_tlb.hh:290
group.hh
gem5::X86ISA::GpuTLB::TLBEvent::virtPageAddr
Addr virtPageAddr
Definition: gpu_tlb.hh:341
gem5::X86ISA::GpuTLB::GpuTLBStats::localNumTLBAccesses
statistics::Scalar localNumTLBAccesses
Definition: gpu_tlb.hh:412
gem5::X86ISA::GpuTLB::numSets
int numSets
Definition: gpu_tlb.hh:120
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::X86ISA::GpuTLB::exitCallback
void exitCallback()
Definition: gpu_tlb.cc:1343
gem5::X86ISA::GpuTLB::cleanup
void cleanup()
Definition: gpu_tlb.cc:1284
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::X86ISA::GpuTLB::outstandingReqs
int outstandingReqs
Definition: gpu_tlb.hh:325
compute_unit.hh
gem5::X86ISA::GpuTLB::AccessInfo::totalReuseDistance
unsigned int totalReuseDistance
Definition: gpu_tlb.hh:382
gem5::X86ISA::GpuTLB::TranslationState::saved
Packet::SenderState * saved
Definition: gpu_tlb.hh:310
tlb.hh
gem5::X86ISA::GpuTLB::TLBEvent::outcome
tlbOutcome outcome
outcome can be TLB_HIT, TLB_MISS, or PAGE_WALK
Definition: gpu_tlb.hh:345
gem5::X86ISA::GpuTLB::walker
Walker * walker
Definition: gpu_tlb.hh:109
gem5::X86ISA::GpuTLB::TLB_MISS
@ TLB_MISS
Definition: gpu_tlb.hh:196
gem5::X86ISA::GpuTLB::Mode
enum BaseMMU::Mode Mode
Definition: gpu_tlb.hh:81
gem5::X86ISA::GpuTLB::MemSidePort::tlb
GpuTLB * tlb
Definition: gpu_tlb.hh:251
gem5::X86ISA::GpuTLB::GpuTLBStats::localTLBMissRate
statistics::Formula localTLBMissRate
Definition: gpu_tlb.hh:415
pagetable_walker.hh
gem5::X86ISA::GpuTLB::CpuSidePort::tlb
GpuTLB * tlb
Definition: gpu_tlb.hh:222
gem5::X86ISA::GpuTLB::TLBEvent::pkt
PacketPtr pkt
Definition: gpu_tlb.hh:346
gem5::X86ISA::GpuTLB::TranslationState::tlbMode
Mode tlbMode
Definition: gpu_tlb.hh:288
gem5::X86ISA::GpuTLB::~GpuTLB
~GpuTLB()
Definition: gpu_tlb.cc:132
gem5::X86ISA::GpuTLB::getWalker
Walker * getWalker()
Definition: gpu_tlb.cc:648
gem5::X86ISA::GpuTLB::GpuTLBStats
Definition: gpu_tlb.hh:406
gem5::X86ISA::GpuTLB::EntryList
std::list< TlbEntry * > EntryList
Definition: gpu_tlb.hh:72
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
std::vector
STL vector class.
Definition: stl.hh:37
gem5::X86ISA::GpuTLB::lookup
TlbEntry * lookup(Addr va, bool update_lru=true)
Definition: gpu_tlb.cc:217
gem5::X86ISA::GpuTLB::TranslationState::issueTime
uint64_t issueTime
Definition: gpu_tlb.hh:301
gem5::X86ISA::Walker
Definition: pagetable_walker.hh:60
gem5::X86ISA::GpuTLB::GpuTLBStats::globalTLBMissRate
statistics::Formula globalTLBMissRate
Definition: gpu_tlb.hh:423
gem5::X86ISA::GpuTLB::FA
bool FA
true if this is a fully-associative TLB
Definition: gpu_tlb.hh:125
gem5::X86ISA::GpuTLB::TLBEvent::getTLBEventVaddr
Addr getTLBEventVaddr()
Definition: gpu_tlb.cc:1016
gem5::X86ISA::GpuTLB::CpuSidePort::recvRespRetry
virtual void recvRespRetry()
Called by the peer if sendTimingResp was called on this protocol (causing recvTimingResp to be called...
Definition: gpu_tlb.hh:230
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::X86ISA::GpuTLB::insert
TlbEntry * insert(Addr vpn, TlbEntry &entry)
Definition: gpu_tlb.cc:161
gem5::X86ISA::GpuTLB::GpuTLBStats::globalNumTLBAccesses
statistics::Scalar globalNumTLBAccesses
Definition: gpu_tlb.hh:420
gem5::X86ISA::GpuTLB::tlbOutcome
tlbOutcome
Definition: gpu_tlb.hh:196
gem5::X86ISA::GpuTLB::lookupIt
EntryList::iterator lookupIt(Addr va, bool update_lru=true)
Definition: gpu_tlb.cc:187
gem5::X86ISA::GpuTLB::CpuSidePort::index
int index
Definition: gpu_tlb.hh:223
request.hh
gem5::X86ISA::GpuTLB::AccessInfo::lastTimeAccessed
unsigned int lastTimeAccessed
Definition: gpu_tlb.hh:379
gem5::X86ISA::GpuTLB::allocationPolicy
bool allocationPolicy
Allocation Policy: true if we always allocate on a hit, false otherwise.
Definition: gpu_tlb.hh:132
gem5::X86ISA::GpuTLB::setConfigAddress
void setConfigAddress(uint32_t addr)
Definition: gpu_tlb.cc:244
gem5::X86ISA::GpuTLB::Translation::finish
virtual void finish(Fault fault, const RequestPtr &req, ThreadContext *tc, Mode mode)=0
The memory for this object may be dynamically allocated, and it may be responsible for cleaning itsle...
gem5::X86ISA::GpuTLB::hasMemSidePort
bool hasMemSidePort
if true, then this is not the last level TLB
Definition: gpu_tlb.hh:137
gem5::X86ISA::GpuTLB::missLatency1
int missLatency1
Definition: gpu_tlb.hh:173
gem5::X86ISA::GpuTLB::TranslationState::isPrefetch
bool isPrefetch
Definition: gpu_tlb.hh:299
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::X86ISA::GpuTLB::GpuTLBStats::localLatency
statistics::Formula localLatency
Definition: gpu_tlb.hh:433
gem5::X86ISA::GpuTLB::cleanupQueue
std::queue< Addr > cleanupQueue
Definition: gpu_tlb.hh:364
gem5::X86ISA::TlbEntry
Definition: pagetable.hh:65
gem5::X86ISA::GpuTLB::CpuSidePort::getAddrRanges
virtual AddrRangeList getAddrRanges() const
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: gpu_tlb.cc:1243
gem5::X86ISA::GpuTLB::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, int &latency)
Definition: gpu_tlb.cc:624
gem5::X86ISA::GpuTLB::serialize
virtual void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: gpu_tlb.cc:655
gem5::X86ISA::GpuTLB::TranslationState
TLB TranslationState: this currently is a somewhat bastardization of the usage of SenderState,...
Definition: gpu_tlb.hh:285
gem5::X86ISA::GpuTLB::TranslationState::hitLevel
int hitLevel
Definition: gpu_tlb.hh:309
gem5::X86ISA::GpuTLB::translate
Fault translate(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, bool &delayedResponse, bool timing, int &latency)
Definition: gpu_tlb.cc:421
gem5::X86ISA::GpuTLB::TranslationState::ports
std::vector< ResponsePort * > ports
Definition: gpu_tlb.hh:303
gem5::X86ISA::GpuTLB::accessDistance
bool accessDistance
Print out accessDistance stats.
Definition: gpu_tlb.hh:143
gem5::X86ISA::GpuTLB::unserialize
virtual void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: gpu_tlb.cc:660
gem5::X86ISA::GpuTLB::handleFuncTranslationReturn
void handleFuncTranslationReturn(PacketPtr pkt, tlbOutcome outcome)
handleFuncTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault retu...
Definition: gpu_tlb.cc:1051
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::X86ISA::GpuTLB::issueTLBLookup
void issueTLBLookup(PacketPtr pkt)
Do the TLB lookup for this coalesced request and schedule another event <TLB access latency> cycles l...
Definition: gpu_tlb.cc:670
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::X86ISA::GpuTLB::GpuTLB
GpuTLB(const Params &p)
Definition: gpu_tlb.cc:68
sim_object.hh
gem5::X86ISA::GpuTLB::CpuSidePort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Receive an atomic request packet from the peer.
Definition: gpu_tlb.hh:226
gem5::Event
Definition: eventq.hh:251
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::X86ISA::GpuTLB::exitEvent
EventFunctionWrapper exitEvent
Definition: gpu_tlb.hh:403
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
statistics.hh
gem5::X86ISA::GpuTLB::doMmuRegRead
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt)
gem5::X86ISA::GpuTLB::Params
X86GPUTLBParams Params
Definition: gpu_tlb.hh:77
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::GpuTLB::updatePageFootprint
void updatePageFootprint(Addr virt_page_addr)
Definition: gpu_tlb.cc:1308
segment.hh
gem5::X86ISA::GpuTLB::translateInt
Fault translateInt(bool read, const RequestPtr &req, ThreadContext *tc)
Definition: gpu_tlb.cc:303
gem5::X86ISA::GpuTLB::TLBEvent
Definition: gpu_tlb.hh:337
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::X86ISA::GpuTLB
Definition: gpu_tlb.hh:67
gem5::X86ISA::GpuTLB::MemSidePort::MemSidePort
MemSidePort(const std::string &_name, GpuTLB *gpu_TLB, PortID _index)
Definition: gpu_tlb.hh:244
gem5::X86ISA::GpuTLB::Translation
Definition: gpu_tlb.hh:83
port.hh
gem5::X86ISA::GpuTLB::tlbLookup
bool tlbLookup(const RequestPtr &req, ThreadContext *tc, bool update_stats)
TLB_lookup will only perform a TLB lookup returning true on a TLB hit and false on a TLB miss.
Definition: gpu_tlb.cc:372
gem5::X86ISA::GpuTLB::MemSidePort
MemSidePort is the TLB Port closer to the memory side If this is a last level TLB then this port will...
Definition: gpu_tlb.hh:241
gem5::X86ISA::GpuTLB::AccessInfo::accessesPerPage
unsigned int accessesPerPage
Definition: gpu_tlb.hh:380
gem5::X86ISA::GpuTLB::dumpAll
void dumpAll()
gem5::X86ISA::GpuTLB::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: gpu_tlb.cc:139
gem5::X86ISA::GpuTLB::GpuTLBStats::globalNumTLBMisses
statistics::Scalar globalNumTLBMisses
Definition: gpu_tlb.hh:422
gem5::X86ISA::GpuTLB::translationReturnEvent
std::unordered_map< Addr, TLBEvent * > translationReturnEvent
Definition: gpu_tlb.hh:360
gem5::X86ISA::GpuTLB::GpuTLBStats::pageTableCycles
statistics::Scalar pageTableCycles
Definition: gpu_tlb.hh:428
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:457
gem5::X86ISA::GpuTLB::CpuSidePort::recvReqRetry
virtual void recvReqRetry()
Definition: gpu_tlb.cc:1235
gem5::X86ISA::GpuTLB::freeList
std::vector< EntryList > freeList
Definition: gpu_tlb.hh:152
gem5::X86ISA::GpuTLB::TranslationState::TranslationState
TranslationState(Mode tlb_mode, ThreadContext *_tc, bool is_prefetch=false, Packet::SenderState *_saved=nullptr)
Definition: gpu_tlb.hh:312
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::GpuTLB::Translation::markDelayed
virtual void markDelayed()=0
Signal that the translation has been delayed due to a hw page table walk.
gem5::X86ISA::GpuTLB::GpuTLBStats::localNumTLBHits
statistics::Scalar localNumTLBHits
Definition: gpu_tlb.hh:413
gem5::X86ISA::GpuTLB::cpuSidePort
std::vector< CpuSidePort * > cpuSidePort
Definition: gpu_tlb.hh:262
gem5::X86ISA::GpuTLB::invalidateNonGlobal
void invalidateNonGlobal()
Definition: gpu_tlb.cc:250
gem5::X86ISA::GpuTLB::CpuSidePort::recvRangeChange
virtual void recvRangeChange()
Definition: gpu_tlb.hh:228
gem5::X86ISA::GpuTLB::GpuTLBStats::localCycles
statistics::Scalar localCycles
Definition: gpu_tlb.hh:431
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Bitfield< 8 > va
Definition: misc_types.hh:275
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::X86ISA::GpuTLB::setMask
Addr setMask
Definition: gpu_tlb.hh:126
gem5::X86ISA::GpuTLB::TLBFootprint
AccessPatternTable TLBFootprint
Definition: gpu_tlb.hh:398
gem5::X86ISA::GpuTLB::entryList
std::vector< EntryList > entryList
An entryList per set is the equivalent of an LRU stack; it's used to guide replacement decisions.
Definition: gpu_tlb.hh:161
gem5::X86ISA::GpuTLB::MemSidePort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
MemSidePort receives the packet back.
Definition: gpu_tlb.cc:1257
gem5::X86ISA::GpuTLB::TLB_HIT
@ TLB_HIT
Definition: gpu_tlb.hh:196
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::X86ISA::GpuTLB::MISS_RETURN
@ MISS_RETURN
Definition: gpu_tlb.hh:196
gem5::X86ISA::GpuTLB::AccessInfo::sumDistance
unsigned int sumDistance
Definition: gpu_tlb.hh:393
gem5::X86ISA::GpuTLB::MemSidePort::retries
std::deque< PacketPtr > retries
Definition: gpu_tlb.hh:248
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A ResponsePort is a specialization of a port.
Definition: port.hh:268
gem5::X86ISA::GpuTLB::TLBEvent::tlb
GpuTLB * tlb
Definition: gpu_tlb.hh:340
gem5::X86ISA::GpuTLB::TLBEvent::process
void process()
Definition: gpu_tlb.cc:998
gem5::X86ISA::GpuTLB::TLBEvent::description
const char * description() const
Return a C string describing the event.
Definition: gpu_tlb.cc:1004
gem5::X86ISA::GpuTLB::hitLatency
int hitLatency
Definition: gpu_tlb.hh:172
gem5::X86ISA::GpuTLB::TranslationState::tlbEntry
TlbEntry * tlbEntry
Definition: gpu_tlb.hh:297
gem5::X86ISA::GpuTLB::TLBEvent::TLBEvent
TLBEvent(GpuTLB *_tlb, Addr _addr, tlbOutcome outcome, PacketPtr _pkt)
Definition: gpu_tlb.cc:750
gem5::X86ISA::GpuTLB::TLBEvent::updateOutcome
void updateOutcome(tlbOutcome _outcome)
Definition: gpu_tlb.cc:1010
gem5::X86ISA::GpuTLB::missLatency2
int missLatency2
Definition: gpu_tlb.hh:174
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Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::X86ISA::GpuTLB::MemSidePort::recvRangeChange
virtual void recvRangeChange()
Called to receive an address range change from the peer response port.
Definition: gpu_tlb.hh:257
gem5::X86ISA::GpuTLB::Translation::~Translation
virtual ~Translation()
Definition: gpu_tlb.hh:86
gem5::X86ISA::GpuTLB::MemSidePort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Definition: gpu_tlb.hh:255
clocked_object.hh
std::deque
STL deque class.
Definition: stl.hh:44
gem5::X86ISA::GpuTLB::pagingProtectionChecks
void pagingProtectionChecks(ThreadContext *tc, PacketPtr pkt, TlbEntry *tlb_entry, Mode mode)
Do Paging protection checks.
Definition: gpu_tlb.cc:762
gem5::X86ISA::GpuTLB::PAGE_WALK
@ PAGE_WALK
Definition: gpu_tlb.hh:196
logging.hh
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::X86ISA::GpuTLB::MemSidePort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Definition: gpu_tlb.hh:256
gem5::X86ISA::GpuTLB::AccessInfo::meanDistance
unsigned int meanDistance
Definition: gpu_tlb.hh:394
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::X86ISA::GpuTLB::AccessPatternTable
std::unordered_map< Addr, AccessInfo > AccessPatternTable
Definition: gpu_tlb.hh:397
gem5::X86ISA::GpuTLB::invalidateAll
void invalidateAll()
Definition: gpu_tlb.cc:230
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::X86ISA::GpuTLB::AccessInfo
This hash map will use the virtual page address as a key and will keep track of total number of acces...
Definition: gpu_tlb.hh:377
gem5::X86ISA::GpuTLB::tlb
std::vector< TlbEntry > tlb
Definition: gpu_tlb.hh:145
gem5::X86ISA::GpuTLB::GpuTLBStats::globalNumTLBHits
statistics::Scalar globalNumTLBHits
Definition: gpu_tlb.hh:421
gem5::X86ISA::GpuTLB::assoc
int assoc
Definition: gpu_tlb.hh:119
std::list< TlbEntry * >
gem5::X86ISA::GpuTLB::CpuSidePort::recvTimingReq
virtual bool recvTimingReq(PacketPtr pkt)
recvTiming receives a coalesced timing request from a TLBCoalescer and it calls issueTLBLookup() It o...
Definition: gpu_tlb.cc:1028
gem5::X86ISA::GpuTLB::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, int &latency)
Definition: gpu_tlb.cc:634
gem5::X86ISA::GpuTLB::handleTranslationReturn
void handleTranslationReturn(Addr addr, tlbOutcome outcome, PacketPtr pkt)
handleTranslationReturn is called on a TLB hit, when a TLB miss returns or when a page fault returns.
Definition: gpu_tlb.cc:797
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::GpuTLB::doMmuRegWrite
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt)
gem5::X86ISA::GpuTLB::MemSidePort::recvReqRetry
virtual void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: gpu_tlb.cc:1276
gem5::X86ISA::GpuTLB::TranslationState::reqCnt
std::vector< int > reqCnt
Definition: gpu_tlb.hh:307
gem5::X86ISA::GpuTLB::demapPage
void demapPage(Addr va, uint64_t asn)
Definition: gpu_tlb.cc:268
gem5::X86ISA::GpuTLB::GpuTLBStats::localNumTLBMisses
statistics::Scalar localNumTLBMisses
Definition: gpu_tlb.hh:414
callback.hh
gem5::Named::_name
const std::string _name
Definition: named.hh:41
gem5::X86ISA::GpuTLB::CpuSidePort
Definition: gpu_tlb.hh:214
gem5::X86ISA::GpuTLB::maxCoalescedReqs
int maxCoalescedReqs
Definition: gpu_tlb.hh:321
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::GpuTLB::cleanupEvent
EventFunctionWrapper cleanupEvent
Definition: gpu_tlb.hh:370
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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