gem5  v21.1.0.2
ide_ctrl.cc
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1 /*
2  * Copyright (c) 2013 ARM Limited
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40 
41 #include "dev/storage/ide_ctrl.hh"
42 
43 #include <string>
44 
45 #include "base/cprintf.hh"
46 #include "debug/IdeCtrl.hh"
47 #include "dev/storage/ide_disk.hh"
48 #include "mem/packet.hh"
49 #include "mem/packet_access.hh"
50 #include "params/IdeController.hh"
51 #include "sim/byteswap.hh"
52 
53 // clang complains about std::set being overloaded with Packet::set if
54 // we open up the entire namespace std
55 using std::string;
56 
57 namespace gem5
58 {
59 
60 // Bus master IDE registers
62 {
63  BMICommand = 0x0,
64  BMIStatus = 0x2,
66 };
67 
68 IdeController::Channel::Channel(string newName) : _name(newName)
69 {
70  bmiRegs.reset();
71  bmiRegs.status.dmaCap0 = 1;
72  bmiRegs.status.dmaCap1 = 1;
73 }
74 
76  : PciDevice(p), configSpaceRegs(name() + ".config_space_regs"),
77  primary(name() + ".primary"),
78  secondary(name() + ".secondary"),
79  ioShift(p.io_shift), ctrlOffset(p.ctrl_offset)
80 {
81 
82  // Assign the disks to channels
83  for (int i = 0; i < params().disks.size(); i++) {
84  if (!params().disks[i])
85  continue;
86  switch (i) {
87  case 0:
88  primary.device0 = params().disks[0];
89  break;
90  case 1:
91  primary.device1 = params().disks[1];
92  break;
93  case 2:
94  secondary.device0 = params().disks[2];
95  break;
96  case 3:
97  secondary.device1 = params().disks[3];
98  break;
99  default:
100  panic("IDE controllers support a maximum "
101  "of 4 devices attached!\n");
102  }
103  // Arbitrarily set the chunk size to 4K.
104  params().disks[i]->setController(this, 4 * 1024);
105  }
106 
107  primary.select(false);
108  secondary.select(false);
109 }
110 
111 void
113 {
114  SERIALIZE_SCALAR(primaryTiming);
115  SERIALIZE_SCALAR(secondaryTiming);
116  SERIALIZE_SCALAR(deviceTiming);
117  SERIALIZE_SCALAR(udmaControl);
118  SERIALIZE_SCALAR(udmaTiming);
119 }
120 
121 void
123 {
124  UNSERIALIZE_SCALAR(primaryTiming);
125  UNSERIALIZE_SCALAR(secondaryTiming);
126  UNSERIALIZE_SCALAR(deviceTiming);
127  UNSERIALIZE_SCALAR(udmaControl);
128  UNSERIALIZE_SCALAR(udmaTiming);
129 }
130 
131 bool
133 {
134  return (primary.selected == diskPtr || secondary.selected == diskPtr);
135 }
136 
137 void
139 {
140  primary.bmiRegs.status.intStatus = 1;
142 }
143 
144 void
146 {
147  Channel *channel;
148  if (disk == primary.device0 || disk == primary.device1) {
149  channel = &primary;
150  } else if (disk == secondary.device0 || disk == secondary.device1) {
151  channel = &secondary;
152  } else {
153  panic("Unable to find disk based on pointer %#x\n", disk);
154  }
155 
156  channel->bmiRegs.command.startStop = 0;
157  channel->bmiRegs.status.active = 0;
158  channel->bmiRegs.status.intStatus = 1;
159 }
160 
161 Tick
163 {
164  int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
166  return PciDevice::readConfig(pkt);
167 
168  size_t size = pkt->getSize();
169 
170  configSpaceRegs.read(offset, pkt->getPtr<void>(), size);
171 
172  DPRINTF(IdeCtrl, "PCI read offset: %#x size: %d data: %#x\n", offset, size,
173  pkt->getUintX(ByteOrder::little));
174 
175  pkt->makeAtomicResponse();
176  return configDelay;
177 }
178 
179 
180 Tick
182 {
183  int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
184 
186  return PciDevice::writeConfig(pkt);
187 
188  size_t size = pkt->getSize();
189 
190  DPRINTF(IdeCtrl, "PCI write offset: %#x size: %d data: %#x\n",
191  offset, size, pkt->getUintX(ByteOrder::little));
192 
193  configSpaceRegs.write(offset, pkt->getConstPtr<void>(), size);
194 
195  pkt->makeAtomicResponse();
196  return configDelay;
197 }
198 
199 void
201  int size, uint8_t *data, bool read)
202 {
203  const Addr SelectOffset = 6;
204  const uint8_t SelectDevBit = 0x10;
205 
206  if (!read && offset == SelectOffset)
207  select(*data & SelectDevBit);
208 
209  if (selected == NULL) {
210  assert(size == sizeof(uint8_t));
211  *data = 0;
212  } else if (read) {
213  selected->readCommand(offset, size, data);
214  } else {
215  selected->writeCommand(offset, size, data);
216  }
217 }
218 
219 void
221  int size, uint8_t *data, bool read)
222 {
223  if (selected == NULL) {
224  assert(size == sizeof(uint8_t));
225  *data = 0;
226  } else if (read) {
227  selected->readControl(offset, size, data);
228  } else {
229  selected->writeControl(offset, size, data);
230  }
231 }
232 
233 void
235  int size, uint8_t *data, bool read)
236 {
237  assert(offset + size <= sizeof(BMIRegs));
238  if (read) {
239  memcpy(data, (uint8_t *)&bmiRegs + offset, size);
240  } else {
241  switch (offset) {
242  case BMICommand:
243  {
244  if (size != sizeof(uint8_t))
245  panic("Invalid BMIC write size: %x\n", size);
246 
247  BMICommandReg oldVal = bmiRegs.command;
248  BMICommandReg newVal = *data;
249 
250  // if a DMA transfer is in progress, R/W control cannot change
251  if (oldVal.startStop && oldVal.rw != newVal.rw)
252  oldVal.rw = newVal.rw;
253 
254  if (oldVal.startStop != newVal.startStop) {
255  if (selected == NULL)
256  panic("DMA start for disk which does not exist\n");
257 
258  if (oldVal.startStop) {
259  DPRINTF(IdeCtrl, "Stopping DMA transfer\n");
260  bmiRegs.status.active = 0;
261 
262  selected->abortDma();
263  } else {
264  DPRINTF(IdeCtrl, "Starting DMA transfer\n");
265  bmiRegs.status.active = 1;
266 
267  selected->startDma(letoh(bmiRegs.bmidtp));
268  }
269  }
270 
271  bmiRegs.command = newVal;
272  }
273  break;
274  case BMIStatus:
275  {
276  if (size != sizeof(uint8_t))
277  panic("Invalid BMIS write size: %x\n", size);
278 
279  BMIStatusReg oldVal = bmiRegs.status;
280  BMIStatusReg newVal = *data;
281 
282  // the BMIDEA bit is read only
283  newVal.active = oldVal.active;
284 
285  // to reset (set 0) IDEINTS and IDEDMAE, write 1 to each
286  if ((oldVal.intStatus == 1) && (newVal.intStatus == 1)) {
287  newVal.intStatus = 0; // clear the interrupt?
288  } else {
289  // Assigning two bitunion fields to each other does not
290  // work as intended, so we need to use this temporary variable
291  // to get around the bug.
292  uint8_t tmp = oldVal.intStatus;
293  newVal.intStatus = tmp;
294  }
295  if ((oldVal.dmaError == 1) && (newVal.dmaError == 1)) {
296  newVal.dmaError = 0;
297  } else {
298  uint8_t tmp = oldVal.dmaError;
299  newVal.dmaError = tmp;
300  }
301 
302  bmiRegs.status = newVal;
303  }
304  break;
305  case BMIDescTablePtr:
306  if (size != sizeof(uint32_t))
307  panic("Invalid BMIDTP write size: %x\n", size);
308  bmiRegs.bmidtp = htole(*(uint32_t *)data & ~0x3);
309  break;
310  default:
311  if (size != sizeof(uint8_t) && size != sizeof(uint16_t) &&
312  size != sizeof(uint32_t))
313  panic("IDE controller write of invalid write size: %x\n", size);
314  memcpy((uint8_t *)&bmiRegs + offset, data, size);
315  }
316  }
317 }
318 
319 void
321 {
322  if (pkt->getSize() != 1 && pkt->getSize() != 2 && pkt->getSize() !=4)
323  panic("Bad IDE read size: %d\n", pkt->getSize());
324 
325  Addr addr = pkt->getAddr();
326  int size = pkt->getSize();
327  uint8_t *dataPtr = pkt->getPtr<uint8_t>();
328 
329  int bar_num;
330  Addr offset;
331  panic_if(!getBAR(addr, bar_num, offset),
332  "IDE controller access to invalid address: %#x.", addr);
333 
334  switch (bar_num) {
335  case 0:
336  // linux may have shifted the address by ioShift,
337  // here we shift it back, similarly for ctrlOffset.
338  offset >>= ioShift;
339  primary.accessCommand(offset, size, dataPtr, read);
340  break;
341  case 1:
342  offset += ctrlOffset;
343  primary.accessControl(offset, size, dataPtr, read);
344  break;
345  case 2:
346  secondary.accessCommand(offset, size, dataPtr, read);
347  break;
348  case 3:
349  secondary.accessControl(offset, size, dataPtr, read);
350  break;
351  case 4:
352  {
353  PciCommandRegister command = letoh(config.command);
354  if (!read && !command.busMaster)
355  return;
356 
357  if (offset < sizeof(Channel::BMIRegs)) {
358  primary.accessBMI(offset, size, dataPtr, read);
359  } else {
360  offset -= sizeof(Channel::BMIRegs);
361  secondary.accessBMI(offset, size, dataPtr, read);
362  }
363  }
364  }
365 
366 #ifndef NDEBUG
367  uint32_t data;
368  if (pkt->getSize() == 1)
369  data = pkt->getLE<uint8_t>();
370  else if (pkt->getSize() == 2)
371  data = pkt->getLE<uint16_t>();
372  else
373  data = pkt->getLE<uint32_t>();
374  DPRINTF(IdeCtrl, "%s from offset: %#x size: %#x data: %#x\n",
375  read ? "Read" : "Write", pkt->getAddr(), pkt->getSize(), data);
376 #endif
377 
378  pkt->makeAtomicResponse();
379 }
380 
381 Tick
383 {
384  dispatchAccess(pkt, true);
385  return pioDelay;
386 }
387 
388 Tick
390 {
391  dispatchAccess(pkt, false);
392  return pioDelay;
393 }
394 
395 void
397 {
398  // Serialize the PciDevice base class
400 
401  // Serialize channels
402  primary.serialize("primary", cp);
403  secondary.serialize("secondary", cp);
404 
405  // Serialize config registers
406  configSpaceRegs.serialize(cp);
407 }
408 
409 void
411  CheckpointOut &cp) const
412 {
413  uint8_t command = bmiRegs.command;
414  paramOut(cp, base + ".bmiRegs.command", command);
415  paramOut(cp, base + ".bmiRegs.reserved0", bmiRegs.reserved0);
416  uint8_t status = bmiRegs.status;
417  paramOut(cp, base + ".bmiRegs.status", status);
418  paramOut(cp, base + ".bmiRegs.reserved1", bmiRegs.reserved1);
419  paramOut(cp, base + ".bmiRegs.bmidtp", bmiRegs.bmidtp);
420  paramOut(cp, base + ".selectBit", selectBit);
421 }
422 
423 void
425 {
426  // Unserialize the PciDevice base class
428 
429  // Unserialize channels
430  primary.unserialize("primary", cp);
431  secondary.unserialize("secondary", cp);
432 
433  // Unserialize config registers
434  configSpaceRegs.unserialize(cp);
435 }
436 
437 void
439 {
440  uint8_t command;
441  paramIn(cp, base +".bmiRegs.command", command);
442  bmiRegs.command = command;
443  paramIn(cp, base + ".bmiRegs.reserved0", bmiRegs.reserved0);
444  uint8_t status;
445  paramIn(cp, base + ".bmiRegs.status", status);
446  bmiRegs.status = status;
447  paramIn(cp, base + ".bmiRegs.reserved1", bmiRegs.reserved1);
448  paramIn(cp, base + ".bmiRegs.bmidtp", bmiRegs.bmidtp);
449  paramIn(cp, base + ".selectBit", selectBit);
450  select(selectBit);
451 }
452 
453 } // namespace gem5
gem5::unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition: thread_context.cc:206
gem5::BMICommand
@ BMICommand
Definition: ide_ctrl.cc:63
gem5::PciDevice::config
PCIConfig config
The current config space.
Definition: device.hh:275
gem5::Packet::getUintX
uint64_t getUintX(ByteOrder endian) const
Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits.
Definition: packet.cc:334
gem5::IdeController::Channel::serialize
void serialize(const std::string &base, std::ostream &os) const
Definition: ide_ctrl.cc:410
data
const char data[]
Definition: circlebuf.test.cc:48
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::PciDevice::serialize
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
Definition: device.cc:401
gem5::PciDevice::unserialize
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: device.cc:464
gem5::IdeController::intrPost
void intrPost()
Definition: ide_ctrl.cc:138
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::PciDevice::pioDelay
Tick pioDelay
Definition: device.hh:354
gem5::IdeController::ctrlOffset
uint32_t ctrlOffset
Definition: ide_ctrl.hh:166
gem5::IdeController::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: ide_ctrl.cc:382
gem5::IdeDisk::readCommand
void readCommand(const Addr offset, int size, uint8_t *data)
Definition: ide_disk.cc:210
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1043
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::IdeController::Channel::select
void select(bool select_device_1)
Definition: ide_ctrl.hh:147
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
PCI_DEVICE_SPECIFIC
#define PCI_DEVICE_SPECIFIC
Definition: pcireg.h:164
gem5::PciDevice::configDelay
Tick configDelay
Definition: device.hh:355
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
packet.hh
gem5::IdeController::ioShift
uint32_t ioShift
Definition: ide_ctrl.hh:166
gem5::PciDevice::writeConfig
virtual Tick writeConfig(PacketPtr pkt)
Write to the PCI config space data that is stored locally.
Definition: device.cc:283
gem5::IdeController::Channel::device0
IdeDisk * device0
IDE disks connected to this controller For more details about device0 and device1 see: https://en....
Definition: ide_ctrl.hh:139
gem5::IdeController::Channel::BMIRegs
Registers used for bus master interface.
Definition: ide_ctrl.hh:118
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::IdeController::Channel::BMIRegs::command
BMICommandReg command
Definition: ide_ctrl.hh:126
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::IdeController::Channel::BMIRegs::status
BMIStatusReg status
Definition: ide_ctrl.hh:128
gem5::IdeController::IdeController
IdeController(const Params &p)
Definition: ide_ctrl.cc:75
gem5::IdeController::secondary
Channel secondary
Definition: ide_ctrl.hh:164
gem5::IdeController::Channel::accessCommand
void accessCommand(Addr offset, int size, uint8_t *data, bool read)
Definition: ide_ctrl.cc:200
gem5::IdeController::dispatchAccess
void dispatchAccess(PacketPtr pkt, bool read)
Definition: ide_ctrl.cc:320
gem5::Packet::getConstPtr
const T * getConstPtr() const
Definition: packet.hh:1193
ide_disk.hh
gem5::PciDevice
PCI device, base implementation is only config space.
Definition: device.hh:269
gem5::PciDevice::getBAR
bool getBAR(Addr addr, int &num, Addr &offs)
Which base address register (if any) maps the given address?
Definition: device.hh:320
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::IdeController::Channel::accessControl
void accessControl(Addr offset, int size, uint8_t *data, bool read)
Definition: ide_ctrl.cc:220
gem5::IdeController::Channel
Definition: ide_ctrl.hh:107
gem5::DmaDevice::Params
DmaDeviceParams Params
Definition: dma_device.hh:209
cprintf.hh
gem5::IdeDisk::writeCommand
void writeCommand(const Addr offset, int size, const uint8_t *data)
Definition: ide_disk.cc:266
gem5::serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:157
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::IdeController::readConfig
Tick readConfig(PacketPtr pkt) override
Read from the PCI config space data that is stored locally.
Definition: ide_ctrl.cc:162
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
packet_access.hh
gem5::BMIDescTablePtr
@ BMIDescTablePtr
Definition: ide_ctrl.cc:65
gem5::IdeController::serialize
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
Definition: ide_ctrl.cc:396
gem5::IdeController::Channel::BMIRegs::reset
void reset()
Definition: ide_ctrl.hh:121
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::PciDevice::readConfig
virtual Tick readConfig(PacketPtr pkt)
Read from the PCI config space data that is stored locally.
Definition: device.cc:212
gem5::paramOut
void paramOut(CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
Definition: types.cc:40
gem5::IdeController::primary
Channel primary
Definition: ide_ctrl.hh:163
gem5::IdeController::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: ide_ctrl.cc:389
gem5::IdeController::setDmaComplete
void setDmaComplete(IdeDisk *disk)
Definition: ide_ctrl.cc:145
gem5::IdeController::Channel::unserialize
void unserialize(const std::string &base, CheckpointIn &cp)
Definition: ide_ctrl.cc:438
gem5::IdeController::isDiskSelected
bool isDiskSelected(IdeDisk *diskPtr)
See if a disk is selected based on its pointer.
Definition: ide_ctrl.cc:132
gem5::IdeController::Channel::selected
IdeDisk * selected
Currently selected disk.
Definition: ide_ctrl.hh:142
gem5::paramIn
void paramIn(CheckpointIn &cp, const std::string &name, ExtMachInst &machInst)
Definition: types.cc:72
gem5::IdeController::Channel::bmiRegs
struct gem5::IdeController::Channel::BMIRegs bmiRegs
gem5::htole
T htole(T value)
Definition: byteswap.hh:172
ide_ctrl.hh
gem5::IdeController::configSpaceRegs
EndBitUnion(BMICommandReg) class ConfigSpaceRegs ConfigSpaceRegs configSpaceRegs
Registers used in device specific PCI configuration.
Definition: ide_ctrl.hh:67
gem5::IdeController::unserialize
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: ide_ctrl.cc:424
gem5::Packet::getLE
T getLE() const
Get the data in the packet byte swapped from little endian to host endian.
Definition: packet_access.hh:78
gem5::IdeController::Channel::accessBMI
void accessBMI(Addr offset, int size, uint8_t *data, bool read)
Definition: ide_ctrl.cc:234
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::IdeDisk
IDE Disk device model.
Definition: ide_disk.hh:216
gem5::IdeController::writeConfig
Tick writeConfig(PacketPtr pkt) override
Write to the PCI config space data that is stored locally.
Definition: ide_ctrl.cc:181
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
PCI_CONFIG_SIZE
#define PCI_CONFIG_SIZE
Definition: pcireg.h:165
gem5::IdeController::Channel::Channel
Channel(std::string newName)
Definition: ide_ctrl.cc:68
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::PciDevice::intrPost
void intrPost()
Definition: device.hh:364
gem5::IdeController::Channel::device1
IdeDisk * device1
Definition: ide_ctrl.hh:139
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::BMIStatus
@ BMIStatus
Definition: ide_ctrl.cc:64
byteswap.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:422
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::Packet::getPtr
T * getPtr()
get a pointer to the data ptr.
Definition: packet.hh:1184
gem5::BMIRegOffset
BMIRegOffset
Definition: ide_ctrl.cc:61

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