gem5  v21.1.0.2
ide_ctrl.hh
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28 
34 #ifndef __DEV_STORAGE_IDE_CTRL_HH__
35 #define __DEV_STORAGE_IDE_CTRL_HH__
36 
37 #include "base/bitunion.hh"
38 #include "dev/io_device.hh"
39 #include "dev/pci/device.hh"
40 #include "dev/reg_bank.hh"
41 #include "params/IdeController.hh"
42 
43 namespace gem5
44 {
45 
46 class IdeDisk;
47 
52 class IdeController : public PciDevice
53 {
54  private:
55  // Bus master IDE status register bit fields
56  BitUnion8(BMIStatusReg)
57  Bitfield<6> dmaCap0;
58  Bitfield<5> dmaCap1;
59  Bitfield<2> intStatus;
60  Bitfield<1> dmaError;
61  Bitfield<0> active;
62  EndBitUnion(BMIStatusReg)
63 
64  BitUnion8(BMICommandReg)
65  Bitfield<3> rw;
66  Bitfield<0> startStop;
67  EndBitUnion(BMICommandReg)
68 
69 
70  class ConfigSpaceRegs : public RegisterBankLE
71  {
72  public:
73  ConfigSpaceRegs(const std::string &name) :
75  {
76  // None of these registers are actually hooked up to control
77  // anything, so they have no specially defined behaviors. They
78  // just store values for now, but should presumably do something
79  // in a more accurate model.
80  addRegisters({primaryTiming, secondaryTiming, deviceTiming, raz0,
81  udmaControl, raz1, udmaTiming, raz2});
82  }
83 
84  enum
85  {
86  TimeRegWithDecodeEnabled = 0x8000
87  };
88 
89  /* Offset in config space */
90  /* 0x40-0x41 */ Register16 primaryTiming =
91  {"primary timing", TimeRegWithDecodeEnabled};
92  /* 0x42-0x43 */ Register16 secondaryTiming =
93  {"secondary timing", TimeRegWithDecodeEnabled};
94  /* 0x44 */ Register8 deviceTiming = {"device timing"};
95  /* 0x45-0x47 */ RegisterRaz raz0 = {"raz0", 3};
96  /* 0x48 */ Register8 udmaControl = {"udma control"};
97  /* 0x49 */ RegisterRaz raz1 = {"raz1", 1};
98  /* 0x4a-0x4b */ Register16 udmaTiming = {"udma timing"};
99  /* 0x4c-... */ RegisterRaz raz2 = {"raz2", PCI_CONFIG_SIZE - 0x4c};
100 
101  void serialize(CheckpointOut &cp) const;
102  void unserialize(CheckpointIn &cp);
103  };
104 
105  ConfigSpaceRegs configSpaceRegs;
106 
107  struct Channel
108  {
109  std::string _name;
110 
111  const std::string
113  {
114  return _name;
115  }
116 
118  struct BMIRegs
119  {
120  void
122  {
123  memset(static_cast<void *>(this), 0, sizeof(*this));
124  }
125 
126  BMICommandReg command;
127  uint8_t reserved0;
128  BMIStatusReg status;
129  uint8_t reserved1;
130  uint32_t bmidtp;
131  } bmiRegs;
132 
139  IdeDisk *device0 = nullptr, *device1 = nullptr;
140 
142  IdeDisk *selected = nullptr;
143 
144  bool selectBit = false;
145 
146  void
147  select(bool select_device_1)
148  {
149  selectBit = select_device_1;
151  }
152 
153  void accessCommand(Addr offset, int size, uint8_t *data, bool read);
154  void accessControl(Addr offset, int size, uint8_t *data, bool read);
155  void accessBMI(Addr offset, int size, uint8_t *data, bool read);
156 
157  Channel(std::string newName);
158 
159  void serialize(const std::string &base, std::ostream &os) const;
160  void unserialize(const std::string &base, CheckpointIn &cp);
161  };
162 
165 
166  uint32_t ioShift, ctrlOffset;
167 
168  void dispatchAccess(PacketPtr pkt, bool read);
169 
170  public:
172  IdeController(const Params &p);
173 
175  bool isDiskSelected(IdeDisk *diskPtr);
176 
177  void intrPost();
178 
179  Tick writeConfig(PacketPtr pkt) override;
180  Tick readConfig(PacketPtr pkt) override;
181 
182  void setDmaComplete(IdeDisk *disk);
183 
184  Tick read(PacketPtr pkt) override;
185  Tick write(PacketPtr pkt) override;
186 
187  void serialize(CheckpointOut &cp) const override;
188  void unserialize(CheckpointIn &cp) override;
189 };
190 
191 } // namespace gem5
192 
193 #endif // __DEV_STORAGE_IDE_CTRL_HH_
io_device.hh
gem5::RegisterBankLE
RegisterBank< ByteOrder::little > RegisterBankLE
Definition: reg_bank.hh:941
gem5::IdeController::Channel::serialize
void serialize(const std::string &base, std::ostream &os) const
Definition: ide_ctrl.cc:410
gem5::IdeController::Channel::BMIRegs::reserved1
uint8_t reserved1
Definition: ide_ctrl.hh:129
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::IdeController::dmaCap1
Bitfield< 5 > dmaCap1
Definition: ide_ctrl.hh:58
gem5::IdeController::intrPost
void intrPost()
Definition: ide_ctrl.cc:138
gem5::IdeController::Channel::BMIRegs::reserved0
uint8_t reserved0
Definition: ide_ctrl.hh:127
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::IdeController::ctrlOffset
uint32_t ctrlOffset
Definition: ide_ctrl.hh:166
gem5::IdeController::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: ide_ctrl.cc:382
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::IdeController::Channel::select
void select(bool select_device_1)
Definition: ide_ctrl.hh:147
device.hh
gem5::IdeController::Channel::name
const std::string name()
Definition: ide_ctrl.hh:112
PCI_DEVICE_SPECIFIC
#define PCI_DEVICE_SPECIFIC
Definition: pcireg.h:164
gem5::IdeController::ioShift
uint32_t ioShift
Definition: ide_ctrl.hh:166
gem5::IdeController::Channel::device0
IdeDisk * device0
IDE disks connected to this controller For more details about device0 and device1 see: https://en....
Definition: ide_ctrl.hh:139
gem5::IdeController::Channel::BMIRegs
Registers used for bus master interface.
Definition: ide_ctrl.hh:118
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::IdeController::Channel::BMIRegs::command
BMICommandReg command
Definition: ide_ctrl.hh:126
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::IdeController::Channel::BMIRegs::status
BMIStatusReg status
Definition: ide_ctrl.hh:128
gem5::IdeController::IdeController
IdeController(const Params &p)
Definition: ide_ctrl.cc:75
bitunion.hh
gem5::IdeController::secondary
Channel secondary
Definition: ide_ctrl.hh:164
gem5::IdeController::Channel::accessCommand
void accessCommand(Addr offset, int size, uint8_t *data, bool read)
Definition: ide_ctrl.cc:200
gem5::IdeController::dispatchAccess
void dispatchAccess(PacketPtr pkt, bool read)
Definition: ide_ctrl.cc:320
gem5::IdeController::Channel::_name
std::string _name
Definition: ide_ctrl.hh:109
gem5::PciDevice
PCI device, base implementation is only config space.
Definition: device.hh:269
gem5::IdeController::PARAMS
PARAMS(IdeController)
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::IdeController::Channel::accessControl
void accessControl(Addr offset, int size, uint8_t *data, bool read)
Definition: ide_ctrl.cc:220
gem5::IdeController::Channel
Definition: ide_ctrl.hh:107
gem5::DmaDevice::Params
DmaDeviceParams Params
Definition: dma_device.hh:209
gem5::IdeController
Device model for an Intel PIIX4 IDE controller.
Definition: ide_ctrl.hh:52
gem5::IdeController::startStop
Bitfield< 0 > startStop
Definition: ide_ctrl.hh:66
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::IdeController::readConfig
Tick readConfig(PacketPtr pkt) override
Read from the PCI config space data that is stored locally.
Definition: ide_ctrl.cc:162
gem5::IdeController::active
Bitfield< 0 > active
Definition: ide_ctrl.hh:61
gem5::IdeController::BitUnion8
BitUnion8(BMIStatusReg) Bitfield< 6 > dmaCap0
gem5::IdeController::serialize
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
Definition: ide_ctrl.cc:396
gem5::IdeController::Channel::BMIRegs::reset
void reset()
Definition: ide_ctrl.hh:121
gem5::IdeController::primary
Channel primary
Definition: ide_ctrl.hh:163
gem5::IdeController::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: ide_ctrl.cc:389
gem5::IdeController::setDmaComplete
void setDmaComplete(IdeDisk *disk)
Definition: ide_ctrl.cc:145
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::IdeController::Channel::unserialize
void unserialize(const std::string &base, CheckpointIn &cp)
Definition: ide_ctrl.cc:438
gem5::IdeController::isDiskSelected
bool isDiskSelected(IdeDisk *diskPtr)
See if a disk is selected based on its pointer.
Definition: ide_ctrl.cc:132
gem5::IdeController::Channel::selectBit
bool selectBit
Definition: ide_ctrl.hh:144
gem5::IdeController::Channel::selected
IdeDisk * selected
Currently selected disk.
Definition: ide_ctrl.hh:142
gem5::IdeController::Channel::bmiRegs
struct gem5::IdeController::Channel::BMIRegs bmiRegs
gem5::RegisterBank< ByteOrder::little >
gem5::IdeController::configSpaceRegs
EndBitUnion(BMICommandReg) class ConfigSpaceRegs ConfigSpaceRegs configSpaceRegs
Registers used in device specific PCI configuration.
Definition: ide_ctrl.hh:67
gem5::IdeController::unserialize
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: ide_ctrl.cc:424
gem5::IdeController::Channel::BMIRegs::bmidtp
uint32_t bmidtp
Definition: ide_ctrl.hh:130
gem5::IdeController::intStatus
Bitfield< 2 > intStatus
Definition: ide_ctrl.hh:59
gem5::IdeController::Channel::accessBMI
void accessBMI(Addr offset, int size, uint8_t *data, bool read)
Definition: ide_ctrl.cc:234
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::IdeDisk
IDE Disk device model.
Definition: ide_disk.hh:216
gem5::ArmISA::rw
Bitfield< 31 > rw
Definition: misc_types.hh:252
gem5::IdeController::writeConfig
Tick writeConfig(PacketPtr pkt) override
Write to the PCI config space data that is stored locally.
Definition: ide_ctrl.cc:181
PCI_CONFIG_SIZE
#define PCI_CONFIG_SIZE
Definition: pcireg.h:165
gem5::IdeController::Channel::Channel
Channel(std::string newName)
Definition: ide_ctrl.cc:68
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::IdeController::EndBitUnion
EndBitUnion(BMIStatusReg) BitUnion8(BMICommandReg) Bitfield< 3 > rw
gem5::IdeController::Channel::device1
IdeDisk * device1
Definition: ide_ctrl.hh:139
gem5::IdeController::dmaError
Bitfield< 1 > dmaError
Definition: ide_ctrl.hh:60
reg_bank.hh

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