ih_mmio.hh File Reference

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Macros
#define	mmIH_RB_CNTL   0x0080
	MMIO offsets for interrupt handler.
#define	mmIH_RB_BASE   0x0081
#define	mmIH_RB_BASE_HI   0x0082
#define	mmIH_RB_RPTR   0x0083
#define	mmIH_RB_WPTR   0x0084
#define	mmIH_RB_WPTR_ADDR_HI   0x0085
#define	mmIH_RB_WPTR_ADDR_LO   0x0086
#define	mmIH_DOORBELL_RPTR   0x0087

Macro Definition Documentation

mmIH_DOORBELL_RPTR

#define mmIH_DOORBELL_RPTR   0x0087

Definition at line 49 of file ih_mmio.hh.

Referenced by gem5::AMDGPUInterruptHandler::writeMMIO().

mmIH_RB_BASE

#define mmIH_RB_BASE   0x0081

Definition at line 43 of file ih_mmio.hh.

Referenced by gem5::AMDGPUInterruptHandler::writeMMIO().

mmIH_RB_BASE_HI

#define mmIH_RB_BASE_HI   0x0082

Definition at line 44 of file ih_mmio.hh.

Referenced by gem5::AMDGPUInterruptHandler::writeMMIO().

mmIH_RB_CNTL

#define mmIH_RB_CNTL   0x0080

MMIO offsets for interrupt handler.

These values were taken from the linux header for IH. The header files can be found here:

https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/blob/roc-4.3.x/ drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_offset.h

Definition at line 42 of file ih_mmio.hh.

Referenced by gem5::AMDGPUInterruptHandler::writeMMIO().

mmIH_RB_RPTR

#define mmIH_RB_RPTR   0x0083

Definition at line 45 of file ih_mmio.hh.

Referenced by gem5::AMDGPUInterruptHandler::writeMMIO().

mmIH_RB_WPTR

#define mmIH_RB_WPTR   0x0084

Definition at line 46 of file ih_mmio.hh.

Referenced by gem5::AMDGPUInterruptHandler::writeMMIO().

mmIH_RB_WPTR_ADDR_HI

#define mmIH_RB_WPTR_ADDR_HI   0x0085

Definition at line 47 of file ih_mmio.hh.

Referenced by gem5::AMDGPUInterruptHandler::writeMMIO().

mmIH_RB_WPTR_ADDR_LO

#define mmIH_RB_WPTR_ADDR_LO   0x0086

Definition at line 48 of file ih_mmio.hh.

Referenced by gem5::AMDGPUInterruptHandler::writeMMIO().