gem5  v22.0.0.1
vecregs.hh
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1 /*
2  * Copyright (c) 2006 The Regents of The University of Michigan
3  * Copyright (c) 2007 MIPS Technologies, Inc.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
8  * met: redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution;
13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28  */
29 
30 #ifndef __ARCH_MIPS_VECREGS_HH__
31 #define __ARCH_MIPS_VECREGS_HH__
32 
34 #include "arch/generic/vec_reg.hh"
35 
36 namespace gem5
37 {
38 
39 namespace MipsISA
40 {
41 
42 // Not applicable to MIPS
45 
46 } // namespace MipsISA
47 } // namespace gem5
48 
49 #endif
vec_pred_reg.hh
vec_reg.hh
gem5::DummyVecPredRegContainer
Dummy type aliases and constants for architectures that do not implement vector predicate registers.
Definition: vec_pred_reg.hh:398
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::DummyVecRegContainer
Dummy type aliases and constants for architectures that do not implement vector registers.
Definition: vec_reg.hh:268

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