gem5  v22.1.0.0
monitor.h
Go to the documentation of this file.
1 /*****************************************************************************
2 
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements. See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License. You may obtain a copy of the License at
9 
10  http://www.apache.org/licenses/LICENSE-2.0
11 
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied. See the License for the specific language governing
16  permissions and limitations under the License.
17 
18  *****************************************************************************/
19 
20 /*****************************************************************************
21 
22  monitor.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 /* Common interface file for monitor process
39  Author: PRP
40  */
41 
42 #include "systemc.h"
43 
44 SC_MODULE( monitor )
45 {
46  SC_HAS_PROCESS( monitor );
47 
48  sc_in_clk clk;
49 
50  // Input Reset Port
51  const sc_signal<bool>& reset_sig;
52 
53  // Input Data Ports
54  const sc_signal<int>& i1;
55  const sc_signal<int>& i2;
56  const sc_signal<int>& i3;
57  const sc_signal<int>& i4;
58  const sc_signal<int>& i5;
59 
60  // Input Control Ports
61  const sc_signal<bool>& cont1;
62  const sc_signal<bool>& cont2;
63  const sc_signal<bool>& cont3;
64 
65  // Input Data Ports
66  const sc_signal<int>& o1;
67  const sc_signal<int>& o2;
68  const sc_signal<int>& o3;
69  const sc_signal<int>& o4;
70  const sc_signal<int>& o5;
71 
72  // Constructor
73  monitor (
74  sc_module_name NAME,
75  sc_clock& CLK,
76 
77  const sc_signal<bool>& RESET_SIG,
78 
79  const sc_signal<int>& I1,
80  const sc_signal<int>& I2,
81  const sc_signal<int>& I3,
82  const sc_signal<int>& I4,
83  const sc_signal<int>& I5,
84 
85  const sc_signal<bool>& CONT1,
86  const sc_signal<bool>& CONT2,
87  const sc_signal<bool>& CONT3,
88 
89  const sc_signal<int>& O1,
90  const sc_signal<int>& O2,
91  const sc_signal<int>& O3,
92  const sc_signal<int>& O4,
93  const sc_signal<int>& O5)
94  : reset_sig(RESET_SIG), i1(I1), i2(I2),
95  i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
96  cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
97  {
98  clk(CLK);
99  SC_CTHREAD( entry, clk.pos() );
100  }
101 
102  void entry();
103 };
SC_MODULE(monitor)
Definition: monitor.h:44
constexpr RegId O5
Definition: int.hh:106
constexpr RegId I1
Definition: int.hh:122
constexpr RegId I4
Definition: int.hh:125
constexpr RegId O1
Definition: int.hh:102
constexpr RegId O4
Definition: int.hh:105
constexpr RegId O3
Definition: int.hh:104
constexpr RegId I5
Definition: int.hh:126
constexpr RegId I3
Definition: int.hh:124
constexpr RegId I2
Definition: int.hh:123
constexpr RegId O2
Definition: int.hh:103
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:323
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:301

Generated on Wed Dec 21 2022 10:22:47 for gem5 by doxygen 1.9.1