gem5 v24.1.0.1
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multiperspective_perceptron_tage.hh
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1/*
2 * Copyright (c) 2022-2023 The University of Edinburgh
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright 2019 Texas A&M University
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions are met:
18 *
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 *
22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 * this list of conditions and the following disclaimer in the documentation
24 * and/or other materials provided with the distribution.
25 *
26 * 3. Neither the name of the copyright holder nor the names of its
27 * contributors may be used to endorse or promote products derived from this
28 * software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Author: Daniel A. Jiménez
43 * Adapted to gem5 by: Javier Bueno Hedo
44 *
45 */
46
47/*
48 * Multiperspective Perceptron Predictor with TAGE (by Daniel A. Jiménez)
49 */
50
51#ifndef __CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_TAGE_HH__
52#define __CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_TAGE_HH__
53
54#include "base/random.hh"
58#include "cpu/pred/tage_base.hh"
59#include "params/MPP_LoopPredictor.hh"
60#include "params/MPP_StatisticalCorrector.hh"
61#include "params/MPP_TAGE.hh"
62#include "params/MultiperspectivePerceptronTAGE.hh"
63
64namespace gem5
65{
66
67namespace branch_prediction
68{
69
70class MPP_TAGE : public TAGEBase
71{
73
75
76 public:
78 {
80 {}
81 virtual ~BranchInfo()
82 {}
83 };
84
85 MPP_TAGE(const MPP_TAGEParams &p) : TAGEBase(p),
87 {}
88
89 void calculateParameters() override;
90 void handleTAGEUpdate(Addr branch_pc, bool taken, TAGEBase::BranchInfo* bi)
91 override;
92 void handleAllocAndUReset(bool alloc, bool taken, TAGEBase::BranchInfo* bi,
93 int nrand) override;
94 void handleUReset() override;
95 void resetUctr(uint8_t &u) override;
96 int bindex(Addr pc_in) const override;
97 bool isHighConfidence(TAGEBase::BranchInfo *bi) const override;
98
99 unsigned getUseAltIdx(TAGEBase::BranchInfo* bi, Addr branch_pc) override;
100 void adjustAlloc(bool & alloc, bool taken, bool pred_taken) override;
101 void updateHistories(ThreadID tid, Addr branch_pc, bool taken,
102 TAGEBase::BranchInfo* b, bool speculative,
103 const StaticInstPtr &inst, Addr target) override;
104
105 void updatePathAndGlobalHistory(ThreadHistory& tHist, int brtype,
106 bool taken, Addr branch_pc, Addr target);
107};
108
110{
111 public:
112 MPP_LoopPredictor(const MPP_LoopPredictorParams &p) : LoopPredictor(p)
113 {}
114
115 bool calcConf(int index) const override;
116 bool optionalAgeInc() const override;
117};
118
120{
121 protected:
122 int8_t thirdH;
123 // global branch history variation GEHL
124 const unsigned pnb;
125 const unsigned logPnb;
129
130 // global branch history GEHL
131 const unsigned gnb;
132 const unsigned logGnb;
136
138 {
141 int64_t globalHist; // global history
144
145 int64_t getHistoryStackEntry() const
146 {
148 }
149
150 void updateHistoryStack(Addr target, bool taken, bool is_call,
151 bool is_return)
152 {
153 unsigned int truncated_target = target;
155 (historyStack[historyStackPointer] << 1) ^ (truncated_target ^
156 (truncated_target >> 5) ^ taken);
157 if (is_return) {
159 historyStack.size();
160 }
161 if (is_call) {
162 int index = (historyStackPointer + 1) % historyStack.size();
165 }
166 }
167 unsigned int getPointer() const { return historyStackPointer; }
168 };
169
170 public:
172 {
173 virtual ~BranchInfo()
174 {}
175 };
176 MPP_StatisticalCorrector(const MPP_StatisticalCorrectorParams &p);
177
178 void initBias() override;
180 bool bias) const override;
182 const override;
183 unsigned getIndBiasBank(Addr branch_pc,
185 int altBank) const override;
186 unsigned getIndUpd(Addr branch_pc) const override;
187 int gIndexLogsSubstr(int nbr, int i) override;
188
189 bool scPredict(ThreadID tid, Addr branch_pc, bool cond_branch,
190 StatisticalCorrector::BranchInfo* bi, bool prev_pred_taken,
191 bool bias_bit, bool use_conf_ctr, int8_t conf_ctr,
192 unsigned conf_bits, int hitBank, int altBank, int64_t phist,
193 int init_lsum) override;
194
195 void condBranchUpdate(ThreadID tid, Addr branch_pc, bool taken,
197 Addr target, bool b, int hitBank, int altBank,
198 int64_t phist) override;
199
200 virtual void getBiasLSUM(Addr branch_pc,
201 StatisticalCorrector::BranchInfo *bi, int &lsum) const = 0;
202
203 void gUpdate(
204 Addr branch_pc, bool taken, int64_t hist, std::vector<int> & length,
205 std::vector<int8_t> * tab, int nbr, int logs,
207};
208
210{
214
240
241 unsigned int getIndex(ThreadID tid, MPPTAGEBranchInfo &bi,
242 const HistorySpec &spec, int index) const;
243 int computePartialSum(ThreadID tid, MPPTAGEBranchInfo &bi) const;
244 void updatePartial(ThreadID tid, MPPTAGEBranchInfo &bi, bool taken);
245 void updateHistories(ThreadID tid, MPPTAGEBranchInfo &bi, bool taken);
246
247 public:
249 const MultiperspectivePerceptronTAGEParams &p);
250
251 void init() override;
252
253 bool lookup(ThreadID tid, Addr instPC, void * &bp_history) override;
254
255 void update(ThreadID tid, Addr pc, bool taken,
256 void * &bp_history, bool squashed,
257 const StaticInstPtr & inst, Addr target) override;
258 void updateHistories(ThreadID tid, Addr pc, bool uncond, bool taken,
259 Addr target, void * &bp_history) override;
260 void squash(ThreadID tid, void * &bp_history) override;
261
262};
263
264} // namespace branch_prediction
265} // namespace gem5
266
267#endif//__CPU_PRED_MULTIPERSPECTIVE_PERCEPTRON_TAGE_HH__
std::shared_ptr< Random > RandomPtr
Definition random.hh:65
static RandomPtr genRandom()
Definition random.hh:68
void gUpdate(Addr branch_pc, bool taken, int64_t hist, std::vector< int > &length, std::vector< int8_t > *tab, int nbr, int logs, std::vector< int8_t > &w, StatisticalCorrector::BranchInfo *bi) override
unsigned getIndBiasSK(Addr branch_pc, StatisticalCorrector::BranchInfo *bi) const override
unsigned getIndBias(Addr branch_pc, StatisticalCorrector::BranchInfo *bi, bool bias) const override
bool scPredict(ThreadID tid, Addr branch_pc, bool cond_branch, StatisticalCorrector::BranchInfo *bi, bool prev_pred_taken, bool bias_bit, bool use_conf_ctr, int8_t conf_ctr, unsigned conf_bits, int hitBank, int altBank, int64_t phist, int init_lsum) override
unsigned getIndBiasBank(Addr branch_pc, StatisticalCorrector::BranchInfo *bi, int hitBank, int altBank) const override
virtual void getBiasLSUM(Addr branch_pc, StatisticalCorrector::BranchInfo *bi, int &lsum) const =0
void condBranchUpdate(ThreadID tid, Addr branch_pc, bool taken, StatisticalCorrector::BranchInfo *bi, Addr target, bool b, int hitBank, int altBank, int64_t phist) override
void handleAllocAndUReset(bool alloc, bool taken, TAGEBase::BranchInfo *bi, int nrand) override
Handles Allocation and U bits reset on an update.
void resetUctr(uint8_t &u) override
Algorithm for resetting a single U counter.
int bindex(Addr pc_in) const override
Computes the index used to access the bimodal table.
void calculateParameters() override
Calculates the history lengths and some other paramters in derived classes.
void updatePathAndGlobalHistory(ThreadHistory &tHist, int brtype, bool taken, Addr branch_pc, Addr target)
void updateHistories(ThreadID tid, Addr branch_pc, bool taken, TAGEBase::BranchInfo *b, bool speculative, const StaticInstPtr &inst, Addr target) override
(Speculatively) updates global histories (path and direction).
void handleTAGEUpdate(Addr branch_pc, bool taken, TAGEBase::BranchInfo *bi) override
Handles the update of the TAGE entries.
bool isHighConfidence(TAGEBase::BranchInfo *bi) const override
void adjustAlloc(bool &alloc, bool taken, bool pred_taken) override
Extra calculation to tell whether TAGE allocaitons may happen or not on an update For this base TAGE ...
unsigned getUseAltIdx(TAGEBase::BranchInfo *bi, Addr branch_pc) override
Calculation of the index for useAltPredForNewlyAllocated On this base TAGE implementation it is alway...
void handleUReset() override
Handles the U bits reset.
bool lookup(ThreadID tid, Addr instPC, void *&bp_history) override
Looks up a given conditional branch PC of in the BP to see if it is taken or not taken.
void update(ThreadID tid, Addr pc, bool taken, void *&bp_history, bool squashed, const StaticInstPtr &inst, Addr target) override
Updates the BP with taken/not taken information.
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
unsigned int getIndex(ThreadID tid, MPPTAGEBranchInfo &bi, const HistorySpec &spec, int index) const
void updatePartial(ThreadID tid, MPPTAGEBranchInfo &bi, bool taken)
void updateHistories(ThreadID tid, MPPTAGEBranchInfo &bi, bool taken)
STL vector class.
Definition stl.hh:37
Bitfield< 7 > b
Bitfield< 7 > i
Definition misc_types.hh:67
Bitfield< 22 > u
Bitfield< 4 > pc
Bitfield< 30, 0 > index
Bitfield< 0 > p
Bitfield< 0 > w
Bitfield< 20, 16 > bi
Definition types.hh:80
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
int16_t ThreadID
Thread index/ID type.
Definition types.hh:235
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
void updateHistoryStack(Addr target, bool taken, bool is_call, bool is_return)
MPPTAGEBranchInfo(Addr pc, int pcshift, bool cond, TAGEBase &tage, LoopPredictor &loopPredictor, StatisticalCorrector &statisticalCorrector)

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