gem5  v22.1.0.0
peripheral.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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20 /*****************************************************************************
21 
22  peripheral.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 #include "common.h"
39 
40 SC_MODULE( peripheral )
41 {
42  SC_HAS_PROCESS( peripheral );
43 
44  sc_in_clk clk;
45 
46  /* Ports( other than clk) */
47  const signal_bool_vector16& mem_addr;
48  const signal_bool_vector8& mem_data_out;
49  signal_bool_vector8& mem_data_in;
50  const sc_signal<bool>& mem_wr_n;
51  const sc_signal<bool>& mem_rd_n;
52  const sc_signal<bool>& mem_pswr_n;
53  const sc_signal<bool>& mem_psrd_n;
54  const sc_signal<bool>& mem_ale;
55  sc_signal<bool>& mem_ea_n;
56 
57  const sc_signal<bool>& p0_mem_reg_n;
58  const sc_signal<bool>& p0_addr_data_n;
59  const sc_signal<bool>& p2_mem_reg_n;
60 
61  peripheral(sc_module_name NAME,
62  sc_clock& TICK,
63  const signal_bool_vector16& MEM_ADDR,
64  const signal_bool_vector8& MEM_DATA_OUT,
65  signal_bool_vector8& MEM_DATA_IN,
66  const sc_signal<bool>& MEM_WR_N,
67  const sc_signal<bool>& MEM_RD_N,
68  const sc_signal<bool>& MEM_PSWR_N,
69  const sc_signal<bool>& MEM_PSRD_N,
70  const sc_signal<bool>& MEM_ALE,
71  sc_signal<bool>& MEM_EA_N,
72 
73  const sc_signal<bool>& P0_MEM_REG_N,
74  const sc_signal<bool>& P0_ADDR_DATA_N,
75  const sc_signal<bool>& P2_MEM_REG_N
76  )
77  :
78  mem_addr(MEM_ADDR),
79  mem_data_out(MEM_DATA_OUT),
80  mem_data_in(MEM_DATA_IN),
81  mem_wr_n(MEM_WR_N),
82  mem_rd_n(MEM_RD_N),
83  mem_pswr_n(MEM_PSWR_N),
84  mem_psrd_n(MEM_PSRD_N),
85  mem_ale(MEM_ALE),
86  mem_ea_n(MEM_EA_N),
87  p0_mem_reg_n(P0_MEM_REG_N),
88  p0_addr_data_n(P0_ADDR_DATA_N),
89  p2_mem_reg_n(P2_MEM_REG_N)
90  {
91  clk(TICK);
92  SC_CTHREAD( entry, clk.pos() );
93  }
94 
95  /* Process functionality in member function below */
96  void entry();
97 };
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
SC_MODULE(peripheral)
Definition: peripheral.h:40
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:323
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:301
sc_signal< sc_bv< 8 > > signal_bool_vector8
Definition: common.h:43
sc_signal< sc_bv< 16 > > signal_bool_vector16
Definition: common.h:44

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