gem5  v21.1.0.2
locked_mem.hh
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45 
46 #ifndef __ARCH_RISCV_LOCKED_MEM_HH__
47 #define __ARCH_RISCV_LOCKED_MEM_HH__
48 
49 #include <stack>
50 #include <unordered_map>
51 
52 #include "base/logging.hh"
53 #include "base/trace.hh"
54 #include "cpu/base.hh"
55 #include "debug/LLSC.hh"
56 #include "mem/packet.hh"
57 #include "mem/request.hh"
58 
59 namespace gem5
60 {
61 
62 /*
63  * ISA-specific helper functions for locked memory accesses.
64  */
65 namespace RiscvISA
66 {
67 
68 const int WARN_FAILURE = 10000;
69 
70 // RISC-V allows multiple locks per hart, but each SC has to unlock the most
71 // recent one, so we use a stack here.
72 extern std::unordered_map<int, std::stack<Addr>> locked_addrs;
73 
74 template <class XC> inline void
75 handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
76 {
77  std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
78 
79  if (locked_addr_stack.empty())
80  return;
81  Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
82  DPRINTF(LLSC, "Locked snoop on address %x.\n", snoop_addr);
83  if ((locked_addr_stack.top() & cacheBlockMask) == snoop_addr)
84  locked_addr_stack.pop();
85 }
86 
87 
88 template <class XC> inline void
89 handleLockedRead(XC *xc, const RequestPtr &req)
90 {
91  std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
92 
93  locked_addr_stack.push(req->getPaddr() & ~0xF);
94  DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
95  req->contextId(), req->getPaddr() & ~0xF);
96 }
97 
98 template <class XC> inline void
100 {}
101 
102 template <class XC> inline bool
103 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
104 {
105  std::stack<Addr>& locked_addr_stack = locked_addrs[xc->contextId()];
106 
107  // Normally RISC-V uses zero to indicate success and nonzero to indicate
108  // failure (right now only 1 is reserved), but in gem5 zero indicates
109  // failure and one indicates success, so here we conform to that (it should
110  // be switched in the instruction's implementation)
111 
112  DPRINTF(LLSC, "[cid:%d]: locked_addrs empty? %s.\n", req->contextId(),
113  locked_addr_stack.empty() ? "yes" : "no");
114  if (!locked_addr_stack.empty()) {
115  DPRINTF(LLSC, "[cid:%d]: addr = %x.\n", req->contextId(),
116  req->getPaddr() & ~0xF);
117  DPRINTF(LLSC, "[cid:%d]: last locked addr = %x.\n", req->contextId(),
118  locked_addr_stack.top());
119  }
120  if (locked_addr_stack.empty()
121  || locked_addr_stack.top() != ((req->getPaddr() & ~0xF))) {
122  req->setExtraData(0);
123  int stCondFailures = xc->readStCondFailures();
124  xc->setStCondFailures(++stCondFailures);
125  if (stCondFailures % WARN_FAILURE == 0) {
126  warn("%i: context %d: %d consecutive SC failures.\n",
127  curTick(), xc->contextId(), stCondFailures);
128  }
129  return false;
130  }
131  if (req->isUncacheable()) {
132  req->setExtraData(2);
133  }
134  return true;
135 }
136 
137 template <class XC>
138 inline void
140 {
141  xc->getCpuPtr()->wakeup(xc->threadId());
142 }
143 
144 } // namespace RiscvISA
145 } // namespace gem5
146 
147 #endif // __ARCH_RISCV_LOCKED_MEM_HH__
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
warn
#define warn(...)
Definition: logging.hh:245
gem5::RiscvISA::handleLockedSnoop
void handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
Definition: locked_mem.hh:75
gem5::RiscvISA::handleLockedSnoopHit
void handleLockedSnoopHit(XC *xc)
Definition: locked_mem.hh:99
gem5::RiscvISA::globalClearExclusive
void globalClearExclusive(XC *xc)
Definition: locked_mem.hh:139
request.hh
packet.hh
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::RiscvISA::handleLockedRead
void handleLockedRead(XC *xc, const RequestPtr &req)
Definition: locked_mem.hh:89
gem5::RiscvISA::locked_addrs
std::unordered_map< int, std::stack< Addr > > locked_addrs
Definition: locked_mem.cc:12
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
base.hh
logging.hh
trace.hh
gem5::RiscvISA::WARN_FAILURE
const int WARN_FAILURE
Definition: locked_mem.hh:68
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RiscvISA::handleLockedWrite
bool handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
Definition: locked_mem.hh:103

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