vecregs.hh

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/*
 * Copyright (c) 2013 ARM Limited
 * Copyright (c) 2014-2015 Sven Karlsson
 * Copyright (c) 2019 Yifei Liu
 * Copyright (c) 2020 Barkhausen Institut
 * Copyright (c) 2021 StreamComputing Corp
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2016 RISC-V Foundation
 * Copyright (c) 2016 The University of Virginia
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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#ifndef __ARCH_RISCV_VECREGS_HH__
#define __ARCH_RISCV_VECREGS_HH__
 
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
 
namespace gem5
{
 
namespace RiscvISA
{
 
// Not applicable to RISC-V
using VecRegContainer = ::gem5::DummyVecRegContainer;
using VecPredRegContainer = ::gem5::DummyVecPredRegContainer;
 
} // namespace RiscvISA
} // namespace gem5
 
#endif // __ARCH_RISCV_VECREGS_HH__