gem5  v21.1.0.2
vecregs.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2013 ARM Limited
3  * Copyright (c) 2014-2015 Sven Karlsson
4  * Copyright (c) 2019 Yifei Liu
5  * Copyright (c) 2020 Barkhausen Institut
6  * Copyright (c) 2021 StreamComputing Corp
7  * All rights reserved
8  *
9  * The license below extends only to copyright in the software and shall
10  * not be construed as granting a license to any other intellectual
11  * property including but not limited to intellectual property relating
12  * to a hardware implementation of the functionality of the software
13  * licensed hereunder. You may use the software subject to the license
14  * terms below provided that you ensure that this notice is replicated
15  * unmodified and in its entirety in all distributions of the software,
16  * modified or unmodified, in source code or in binary form.
17  *
18  * Copyright (c) 2016 RISC-V Foundation
19  * Copyright (c) 2016 The University of Virginia
20  * All rights reserved.
21  *
22  * Redistribution and use in source and binary forms, with or without
23  * modification, are permitted provided that the following conditions are
24  * met: redistributions of source code must retain the above copyright
25  * notice, this list of conditions and the following disclaimer;
26  * redistributions in binary form must reproduce the above copyright
27  * notice, this list of conditions and the following disclaimer in the
28  * documentation and/or other materials provided with the distribution;
29  * neither the name of the copyright holders nor the names of its
30  * contributors may be used to endorse or promote products derived from
31  * this software without specific prior written permission.
32  *
33  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44  */
45 
46 #ifndef __ARCH_RISCV_VECREGS_HH__
47 #define __ARCH_RISCV_VECREGS_HH__
48 
49 #include <cstdint>
50 
52 #include "arch/generic/vec_reg.hh"
53 
54 namespace gem5
55 {
56 
57 namespace RiscvISA
58 {
59 
60 // Not applicable to RISC-V
64 
65 // Not applicable to RISC-V
67 
68 } // namespace RiscvISA
69 } // namespace gem5
70 
71 #endif // __ARCH_RISCV_VECREGS_HH__
gem5::RiscvISA::VecElem
::gem5::DummyVecElem VecElem
Definition: vecregs.hh:61
gem5::VecPredRegContainer
Generic predicate register container.
Definition: vec_pred_reg.hh:53
gem5::DummyVecElem
uint32_t DummyVecElem
Dummy type aliases and constants for architectures that do not implement vector registers.
Definition: vec_reg.hh:266
gem5::RiscvISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vecregs.hh:63
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:121
vec_pred_reg.hh
vec_reg.hh
gem5::DummyVecRegContainer
VecRegContainer< DummyNumVecElemPerVecReg *sizeof(DummyVecElem)> DummyVecRegContainer
Definition: vec_reg.hh:269
gem5::DummyNumVecElemPerVecReg
constexpr unsigned DummyNumVecElemPerVecReg
Definition: vec_reg.hh:267
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::DummyVecPredRegContainer
VecPredRegContainer< 8, false > DummyVecPredRegContainer
Dummy type aliases and constants for architectures that do not implement vector predicate registers.
Definition: vec_pred_reg.hh:395

Generated on Tue Sep 21 2021 12:24:47 for gem5 by doxygen 1.8.17