gem5  v22.0.0.1
vecregs.hh
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28 
29 #ifndef __ARCH_SPARC_VECREGS_HH__
30 #define __ARCH_SPARC_VECREGS_HH__
31 
33 #include "arch/generic/vec_reg.hh"
34 
35 namespace gem5
36 {
37 
38 namespace SparcISA
39 {
40 
41 // Not applicable to SPARC
44 
45 } // namespace SparcISA
46 } // namespace gem5
47 
48 #endif
vec_pred_reg.hh
vec_reg.hh
gem5::DummyVecPredRegContainer
Dummy type aliases and constants for architectures that do not implement vector predicate registers.
Definition: vec_pred_reg.hh:398
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::DummyVecRegContainer
Dummy type aliases and constants for architectures that do not implement vector registers.
Definition: vec_reg.hh:268

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