gem5 v24.0.0.0
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regfile.h
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1/*****************************************************************************
2
3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4 more contributor license agreements. See the NOTICE file distributed
5 with this work for additional information regarding copyright ownership.
6 Accellera licenses this file to you under the Apache License, Version 2.0
7 (the "License"); you may not use this file except in compliance with the
8 License. You may obtain a copy of the License at
9
10 http://www.apache.org/licenses/LICENSE-2.0
11
12 Unless required by applicable law or agreed to in writing, software
13 distributed under the License is distributed on an "AS IS" BASIS,
14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22 regfile.h --
23
24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31 changes you are making here.
32
33 Name, Affiliation, Date:
34 Description of Modification:
35
36 *****************************************************************************/
37
38struct test : sc_module {
39
40 sc_in<bool> reset;
42 sc_in<sc_lv<14> > dati;
43 sc_out<sc_lv<14> > dato;
44 sc_out<sc_logic> ready, done;
45
47
48 test (const char *NAME) : sc_module(NAME) {
49 SC_CTHREAD( reset_loop, clk.pos() );
50 reset_signal_is(reset,true);
51 end_module();
52 }
53
54 void reset_loop();
55};
56
sc_in< bool > sc_in_clk
Definition sc_clock.hh:116
#define SC_CTHREAD(name, clk)
Definition sc_module.hh:323
Definition test.h:38
sc_out< sc_uint< 8 > > dato
Definition test.h:43
SC_HAS_PROCESS(test)
sc_in_clk clk
Definition test.h:41
test(const char *NAME)
Definition regfile.h:48
sc_out< sc_logic > ready
Definition regfile.h:44
sc_in< sc_uint< 8 > > dati
Definition test.h:42
void reset_loop()
sc_out< bool > done
Definition test.h:44
sc_in< bool > reset
Definition test.h:40

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