gem5::Gcn3ISA::InFmt_MIMG Struct Reference

#include <gpu_decoder.hh>

Public Attributes
unsigned int	pad_0_7: 8
unsigned int	DMASK: 4
unsigned int	UNORM: 1
unsigned int	GLC: 1
unsigned int	DA: 1
unsigned int	R128: 1
unsigned int	TFE: 1
unsigned int	LWE: 1
unsigned int	OP: 7
unsigned int	SLC: 1
unsigned int	ENCODING: 6

Detailed Description

Definition at line 1416 of file gpu_decoder.hh.

Member Data Documentation

DA

unsigned int gem5::Gcn3ISA::InFmt_MIMG::DA

Definition at line 1422 of file gpu_decoder.hh.

DMASK

unsigned int gem5::Gcn3ISA::InFmt_MIMG::DMASK

Definition at line 1419 of file gpu_decoder.hh.

ENCODING

unsigned int gem5::Gcn3ISA::InFmt_MIMG::ENCODING

Definition at line 1428 of file gpu_decoder.hh.

GLC

unsigned int gem5::Gcn3ISA::InFmt_MIMG::GLC

Definition at line 1421 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_MIMG::Inst_MIMG(), gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_ADD::Inst_MIMG__IMAGE_ATOMIC_ADD(), gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_AND::Inst_MIMG__IMAGE_ATOMIC_AND(), gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_CMPSWAP::Inst_MIMG__IMAGE_ATOMIC_CMPSWAP(), gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_DEC::Inst_MIMG__IMAGE_ATOMIC_DEC(), gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_INC::Inst_MIMG__IMAGE_ATOMIC_INC(), gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_OR::Inst_MIMG__IMAGE_ATOMIC_OR(), gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_SMAX::Inst_MIMG__IMAGE_ATOMIC_SMAX(), gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_SMIN::Inst_MIMG__IMAGE_ATOMIC_SMIN(), gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_SUB::Inst_MIMG__IMAGE_ATOMIC_SUB(), gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_SWAP::Inst_MIMG__IMAGE_ATOMIC_SWAP(), gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_UMAX::Inst_MIMG__IMAGE_ATOMIC_UMAX(), gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_UMIN::Inst_MIMG__IMAGE_ATOMIC_UMIN(), and gem5::Gcn3ISA::Inst_MIMG__IMAGE_ATOMIC_XOR::Inst_MIMG__IMAGE_ATOMIC_XOR().

LWE

unsigned int gem5::Gcn3ISA::InFmt_MIMG::LWE

Definition at line 1425 of file gpu_decoder.hh.

OP

unsigned int gem5::Gcn3ISA::InFmt_MIMG::OP

Definition at line 1426 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Decoder::subDecode_OP_MIMG().

pad_0_7

unsigned int gem5::Gcn3ISA::InFmt_MIMG::pad_0_7

Definition at line 1418 of file gpu_decoder.hh.

R128

unsigned int gem5::Gcn3ISA::InFmt_MIMG::R128

Definition at line 1423 of file gpu_decoder.hh.

SLC

unsigned int gem5::Gcn3ISA::InFmt_MIMG::SLC

Definition at line 1427 of file gpu_decoder.hh.

Referenced by gem5::Gcn3ISA::Inst_MIMG::Inst_MIMG().

TFE

unsigned int gem5::Gcn3ISA::InFmt_MIMG::TFE

Definition at line 1424 of file gpu_decoder.hh.

UNORM

unsigned int gem5::Gcn3ISA::InFmt_MIMG::UNORM

Definition at line 1420 of file gpu_decoder.hh.

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The documentation for this struct was generated from the following file:

• arch/amdgpu/gcn3/gpu_decoder.hh