gem5  v21.2.0.0
tlb_coalescer.hh
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31 
32 #ifndef __TLB_COALESCER_HH__
33 #define __TLB_COALESCER_HH__
34 
35 #include <list>
36 #include <queue>
37 #include <string>
38 #include <vector>
39 
41 #include "arch/generic/tlb.hh"
42 #include "arch/x86/isa.hh"
43 #include "arch/x86/pagetable.hh"
44 #include "arch/x86/regs/segment.hh"
45 #include "base/logging.hh"
46 #include "base/statistics.hh"
47 #include "mem/port.hh"
48 #include "mem/request.hh"
49 #include "params/TLBCoalescer.hh"
50 #include "sim/clocked_object.hh"
51 
52 namespace gem5
53 {
54 
55 class BaseTLB;
56 class Packet;
57 class ThreadContext;
58 
67 {
68  public:
69  typedef TLBCoalescerParams Params;
70  TLBCoalescer(const Params &p);
72 
73  // Number of TLB probes per cycle. Parameterizable - default 2.
75 
76  // Consider coalescing across that many ticks.
77  // Paraemterizable - default 1.
79 
80  // Each coalesced request consists of multiple packets
81  // that all fall within the same virtual page
83 
84  // disables coalescing when true
86 
87  /*
88  * This is a hash map with <tick_index> as a key.
89  * It contains a vector of coalescedReqs per <tick_index>.
90  * Requests are buffered here until they can be issued to
91  * the TLB, at which point they are copied to the
92  * issuedTranslationsTable hash map.
93  *
94  * In terms of coalescing, we coalesce requests in a given
95  * window of x cycles by using tick_index = issueTime/x as a
96  * key, where x = coalescingWindow. issueTime is the issueTime
97  * of the pkt from the ComputeUnit's perspective, but another
98  * option is to change it to curTick(), so we coalesce based
99  * on the receive time.
100  */
101  typedef std::map<int64_t, std::vector<coalescedReq>>
103 
105 
106  /*
107  * issuedTranslationsTabler: a hash_map indexed by virtual page
108  * address. Each hash_map entry has a vector of PacketPtr associated
109  * with it denoting the different packets that share an outstanding
110  * coalesced translation request for the same virtual page.
111  *
112  * The rules that determine which requests we can coalesce are
113  * specified in the canCoalesce() method.
114  */
115  typedef std::unordered_map<Addr, coalescedReq> CoalescingTable;
116 
118 
119  bool canCoalesce(PacketPtr pkt1, PacketPtr pkt2);
120  void updatePhysAddresses(PacketPtr pkt);
121 
122  class CpuSidePort : public ResponsePort
123  {
124  public:
125  CpuSidePort(const std::string &_name, TLBCoalescer *tlb_coalescer,
126  PortID _index)
127  : ResponsePort(_name, tlb_coalescer), coalescer(tlb_coalescer),
128  index(_index) { }
129 
130  protected:
132  int index;
133 
134  virtual bool recvTimingReq(PacketPtr pkt);
135  virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
136  virtual void recvFunctional(PacketPtr pkt);
137  virtual void recvRangeChange() { }
138  virtual void recvReqRetry();
139 
140  virtual void
142  {
143  fatal("recvRespRetry() is not implemented in the TLB "
144  "coalescer.\n");
145  }
146 
147  virtual AddrRangeList getAddrRanges() const;
148  };
149 
150  class MemSidePort : public RequestPort
151  {
152  public:
153  MemSidePort(const std::string &_name, TLBCoalescer *tlb_coalescer,
154  PortID _index)
155  : RequestPort(_name, tlb_coalescer), coalescer(tlb_coalescer),
156  index(_index) { }
157 
159 
160  protected:
162  int index;
163 
164  virtual bool recvTimingResp(PacketPtr pkt);
165  virtual Tick recvAtomic(PacketPtr pkt) { return 0; }
166  virtual void recvFunctional(PacketPtr pkt);
167  virtual void recvRangeChange() { }
168  virtual void recvReqRetry();
169 
170  virtual void
172  {
173  fatal("recvRespRetry() not implemented in TLB coalescer");
174  }
175  };
176 
177  // Coalescer response ports on the cpu Side
179  // Coalescer request ports on the memory side
181 
182  Port &getPort(const std::string &if_name,
183  PortID idx=InvalidPortID) override;
184 
185  void processProbeTLBEvent();
188 
189  void processCleanupEvent();
193 
194  // this FIFO queue keeps track of the virt. page
195  // addresses that are pending cleanup
196  std::queue<Addr> cleanupQueue;
197 
198  protected:
200  {
202 
203  // number of packets the coalescer receives
205  // number packets the coalescer send to the TLB
207 
208  // Number of cycles the coalesced requests spend waiting in
209  // coalescerFIFO. For each packet the coalescer receives we take into
210  // account the number of all uncoalesced requests this pkt "represents"
212 
213  // On average how much time a request from the
214  // uncoalescedAccesses that reaches the TLB
215  // spends waiting?
217  // localqueuingCycles/uncoalescedAccesses
219  } stats;
220 };
221 
222 } // namespace gem5
223 
224 #endif // __TLB_COALESCER_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::TLBCoalescer::TLBCoalescerStats::queuingCycles
statistics::Scalar queuingCycles
Definition: tlb_coalescer.hh:211
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
pagetable.hh
gem5::TLBCoalescer::CpuSidePort::recvTimingReq
virtual bool recvTimingReq(PacketPtr pkt)
Receive a timing request from the peer.
Definition: tlb_coalescer.cc:230
gem5::TLBCoalescer::CpuSidePort::recvRangeChange
virtual void recvRangeChange()
Definition: tlb_coalescer.hh:137
gem5::TLBCoalescer::MemSidePort::MemSidePort
MemSidePort(const std::string &_name, TLBCoalescer *tlb_coalescer, PortID _index)
Definition: tlb_coalescer.hh:153
gem5::TLBCoalescer::CpuSidePort::recvReqRetry
virtual void recvReqRetry()
Definition: tlb_coalescer.cc:329
gem5::TLBCoalescer::processCleanupEvent
void processCleanupEvent()
Definition: tlb_coalescer.cc:513
gem5::TLBCoalescer::MemSidePort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Definition: tlb_coalescer.hh:165
gem5::TLBCoalescer::MemSidePort::index
int index
Definition: tlb_coalescer.hh:162
gem5::TLBCoalescer::CpuSidePort::index
int index
Definition: tlb_coalescer.hh:132
gem5::TLBCoalescer::issuedTranslationsTable
CoalescingTable issuedTranslationsTable
Definition: tlb_coalescer.hh:117
gem5::TLBCoalescer::~TLBCoalescer
~TLBCoalescer()
Definition: tlb_coalescer.hh:71
tlb.hh
gem5::TLBCoalescer::TLBProbesPerCycle
int TLBProbesPerCycle
Definition: tlb_coalescer.hh:74
gem5::TLBCoalescer::cleanupQueue
std::queue< Addr > cleanupQueue
Definition: tlb_coalescer.hh:196
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2539
std::vector
STL vector class.
Definition: stl.hh:37
gem5::TLBCoalescer::memSidePort
std::vector< MemSidePort * > memSidePort
Definition: tlb_coalescer.hh:180
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
gem5::TLBCoalescer::processProbeTLBEvent
void processProbeTLBEvent()
Definition: tlb_coalescer.cc:407
request.hh
gem5::TLBCoalescer::TLBCoalescerStats
Definition: tlb_coalescer.hh:199
gem5::TLBCoalescer::MemSidePort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Definition: tlb_coalescer.cc:389
gem5::TLBCoalescer::CpuSidePort::coalescer
TLBCoalescer * coalescer
Definition: tlb_coalescer.hh:131
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::TLBCoalescer::MemSidePort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: tlb_coalescer.cc:371
gem5::TLBCoalescer::MemSidePort::recvRespRetry
virtual void recvRespRetry()
Definition: tlb_coalescer.hh:171
gem5::TLBCoalescer::TLBCoalescer
TLBCoalescer(const Params &p)
Definition: tlb_coalescer.cc:44
gem5::TLBCoalescer::MemSidePort::recvRangeChange
virtual void recvRangeChange()
Called to receive an address range change from the peer response port.
Definition: tlb_coalescer.hh:167
gem5::TLBCoalescer::updatePhysAddresses
void updatePhysAddresses(PacketPtr pkt)
Definition: tlb_coalescer.cc:142
gem5::TLBCoalescer::CoalescingFIFO
std::map< int64_t, std::vector< coalescedReq > > CoalescingFIFO
Definition: tlb_coalescer.hh:102
gem5::TLBCoalescer::MemSidePort::recvReqRetry
virtual void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: tlb_coalescer.cc:380
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
statistics.hh
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
segment.hh
gem5::TLBCoalescer::coalescedReq
std::vector< PacketPtr > coalescedReq
Definition: tlb_coalescer.hh:82
gem5::TLBCoalescer::MemSidePort::coalescer
TLBCoalescer * coalescer
Definition: tlb_coalescer.hh:161
port.hh
gem5::TLBCoalescer::CpuSidePort
Definition: tlb_coalescer.hh:122
gem5::TLBCoalescer::CoalescingTable
std::unordered_map< Addr, coalescedReq > CoalescingTable
Definition: tlb_coalescer.hh:115
gem5::TLBCoalescer::CpuSidePort::getAddrRanges
virtual AddrRangeList getAddrRanges() const
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: tlb_coalescer.cc:362
gem5::TLBCoalescer::TLBCoalescerStats::localLatency
statistics::Formula localLatency
Definition: tlb_coalescer.hh:218
gem5::TLBCoalescer::cpuSidePort
std::vector< CpuSidePort * > cpuSidePort
Definition: tlb_coalescer.hh:178
gem5::TLBCoalescer::cleanupEvent
EventFunctionWrapper cleanupEvent
The cleanupEvent is scheduled after a TLBEvent triggers in order to free memory and do the required c...
Definition: tlb_coalescer.hh:192
gem5::TLBCoalescer::canCoalesce
bool canCoalesce(PacketPtr pkt1, PacketPtr pkt2)
Definition: tlb_coalescer.cc:97
gem5::TLBCoalescer::coalescerFIFO
CoalescingFIFO coalescerFIFO
Definition: tlb_coalescer.hh:104
gem5::TLBCoalescer::CpuSidePort::recvRespRetry
virtual void recvRespRetry()
Called by the peer if sendTimingResp was called on this protocol (causing recvTimingResp to be called...
Definition: tlb_coalescer.hh:141
tlb.hh
gem5::TLBCoalescer::TLBCoalescerStats::localqueuingCycles
statistics::Scalar localqueuingCycles
Definition: tlb_coalescer.hh:216
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::TLBCoalescer
The TLBCoalescer is a ClockedObject sitting on the front side (CPUSide) of each TLB.
Definition: tlb_coalescer.hh:66
isa.hh
gem5::TLBCoalescer::CpuSidePort::CpuSidePort
CpuSidePort(const std::string &_name, TLBCoalescer *tlb_coalescer, PortID _index)
Definition: tlb_coalescer.hh:125
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::TLBCoalescer::probeTLBEvent
EventFunctionWrapper probeTLBEvent
This event issues the TLB probes.
Definition: tlb_coalescer.hh:187
gem5::ResponsePort
A ResponsePort is a specialization of a port.
Definition: port.hh:268
gem5::TLBCoalescer::TLBCoalescerStats::uncoalescedAccesses
statistics::Scalar uncoalescedAccesses
Definition: tlb_coalescer.hh:204
gem5::TLBCoalescer::TLBCoalescerStats::coalescedAccesses
statistics::Scalar coalescedAccesses
Definition: tlb_coalescer.hh:206
gem5::TLBCoalescer::MemSidePort::retries
std::deque< PacketPtr > retries
Definition: tlb_coalescer.hh:158
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::TLBCoalescer::MemSidePort
Definition: tlb_coalescer.hh:150
gem5::TLBCoalescer::stats
gem5::TLBCoalescer::TLBCoalescerStats stats
clocked_object.hh
std::deque
STL deque class.
Definition: stl.hh:44
gem5::TLBCoalescer::Params
TLBCoalescerParams Params
Definition: tlb_coalescer.hh:69
logging.hh
gem5::TLBCoalescer::TLBCoalescerStats::TLBCoalescerStats
TLBCoalescerStats(statistics::Group *parent)
Definition: tlb_coalescer.cc:525
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::TLBCoalescer::disableCoalescing
bool disableCoalescing
Definition: tlb_coalescer.hh:85
gem5::TLBCoalescer::CpuSidePort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Receive an atomic request packet from the peer.
Definition: tlb_coalescer.hh:135
std::list< AddrRange >
gem5::TLBCoalescer::CpuSidePort::recvFunctional
virtual void recvFunctional(PacketPtr pkt)
Receive a functional request packet from the peer.
Definition: tlb_coalescer.cc:335
gem5::TLBCoalescer::coalescingWindow
int coalescingWindow
Definition: tlb_coalescer.hh:78
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::TLBCoalescer::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: tlb_coalescer.cc:71
gem5::Named::_name
const std::string _name
Definition: named.hh:41

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