55 sc_signal<bool>& ready;
58 stimgen (sc_module_name NAME,
63 sc_signal<bool>& READY )
#define SC_CTHREAD(name, clk)
#define SC_HAS_PROCESS(name)
sc_signal< bool_vector4 > signal_bool_vector4
sc_signal< bool_vector7 > signal_bool_vector7
sc_signal< bool_vector6 > signal_bool_vector6