gem5  v22.1.0.0
gpu_isa.hh
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31 
32 #ifndef __ARCH_VEGA_GPU_ISA_HH__
33 #define __ARCH_VEGA_GPU_ISA_HH__
34 
35 #include <array>
36 #include <type_traits>
37 
39 #include "arch/amdgpu/vega/tlb.hh"
42 #include "gpu-compute/misc.hh"
43 
44 namespace gem5
45 {
46 
47 class Wavefront;
48 
49 namespace VegaISA
50 {
51  class GPUISA
52  {
53  public:
54  GPUISA(Wavefront &wf);
55 
56  template<typename T> T
57  readConstVal(int opIdx) const
58  {
59  panic_if(!std::is_integral_v<T>,
60  "Constant values must be an integer.");
61  T val(0);
62 
63  if (isPosConstVal(opIdx)) {
64  val = (T)readPosConstReg(opIdx);
65  }
66 
67  if (isNegConstVal(opIdx)) {
68  val = (T)readNegConstReg(opIdx);
69  }
70 
71  return val;
72  }
73 
74  ScalarRegU32 readMiscReg(int opIdx) const;
75  void writeMiscReg(int opIdx, ScalarRegU32 operandVal);
76  bool hasScalarUnit() const { return true; }
77  void advancePC(GPUDynInstPtr gpuDynInst);
78 
79  private:
80  ScalarRegU32 readPosConstReg(int opIdx) const
81  {
82  return posConstRegs[opIdx - REG_INT_CONST_POS_MIN];
83  }
84 
85  ScalarRegI32 readNegConstReg(int opIdx) const
86  {
87  return negConstRegs[opIdx - REG_INT_CONST_NEG_MIN];
88  }
89 
90  static const std::array<const ScalarRegU32, NumPosConstRegs>
92  static const std::array<const ScalarRegI32, NumNegConstRegs>
94 
95  // parent wavefront
97 
98  // shader status bits
100  // memory descriptor reg
102  };
103 } // namespace VegaISA
104 } // namespace gem5
105 
106 #endif // __ARCH_VEGA_GPU_ISA_HH__
static const std::array< const ScalarRegU32, NumPosConstRegs > posConstRegs
Definition: gpu_isa.hh:91
ScalarRegU32 readMiscReg(int opIdx) const
Definition: isa.cc:49
bool hasScalarUnit() const
Definition: gpu_isa.hh:76
ScalarRegU32 readPosConstReg(int opIdx) const
Definition: gpu_isa.hh:80
void advancePC(GPUDynInstPtr gpuDynInst)
Definition: isa.cc:83
Wavefront & wavefront
Definition: gpu_isa.hh:96
ScalarRegU32 m0
Definition: gpu_isa.hh:101
void writeMiscReg(int opIdx, ScalarRegU32 operandVal)
Definition: isa.cc:66
GPUISA(Wavefront &wf)
Definition: isa.cc:44
T readConstVal(int opIdx) const
Definition: gpu_isa.hh:57
StatusReg statusReg
Definition: gpu_isa.hh:99
ScalarRegI32 readNegConstReg(int opIdx) const
Definition: gpu_isa.hh:85
static const std::array< const ScalarRegI32, NumNegConstRegs > negConstRegs
Definition: gpu_isa.hh:93
The GPUDispatcher is the component of the shader that is responsible for creating and dispatching WGs...
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
HSAQueuEntry is the simulator's internal representation of an AQL queue entry (task).
bool isNegConstVal(int opIdx)
Definition: registers.cc:188
int32_t ScalarRegI32
bool isPosConstVal(int opIdx)
Definition: registers.cc:179
uint32_t ScalarRegU32
Bitfield< 63 > val
Definition: misc.hh:776
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:49

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