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gem5
v22.1.0.0
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#include "arch/amdgpu/vega/gpu_registers.hh"Go to the source code of this file.
Namespaces | |
| gem5 | |
| Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223. | |
| gem5::VegaISA | |
| classes that represnt vector/scalar operands in VEGA ISA. | |
Functions | |
| std::string | gem5::VegaISA::opSelectorToRegSym (int opIdx, int numRegs=0) |
| int | gem5::VegaISA::opSelectorToRegIdx (int opIdx, int numScalarRegs) |
| bool | gem5::VegaISA::isPosConstVal (int opIdx) |
| bool | gem5::VegaISA::isNegConstVal (int opIdx) |
| bool | gem5::VegaISA::isConstVal (int opIdx) |
| bool | gem5::VegaISA::isLiteral (int opIdx) |
| bool | gem5::VegaISA::isExecMask (int opIdx) |
| bool | gem5::VegaISA::isVccReg (int opIdx) |
| bool | gem5::VegaISA::isFlatScratchReg (int opIdx) |
| bool | gem5::VegaISA::isScalarReg (int opIdx) |
| bool | gem5::VegaISA::isVectorReg (int opIdx) |