Here is a list of all namespace members with links to the namespace documentation for each member:

- r -

r : MipsISA , RiscvISA
R : X86ISA
r : X86ISA
r0 : MipsISA , RiscvISA
ra : PowerISA
random : MipsISA , RiscvISA
rao2 : ArmISA
rao3 : ArmISA
rao4 : ArmISA
ras : ArmISA
RawMachInst : Gcn3ISA , HsailISA
raz : ArmISA
raz_13_4 : ArmISA
raz_28 : ArmISA
rc31 : PowerISA
RCV_ADDRESS_TABLE_SIZE : iGbReg
rd : ArmISA , X86ISA
rdm : ArmISA
re : MipsISA , RiscvISA
RE : X86ISA
readable : X86ISA
ReadData : Ps2::Mouse
readDSPControl() : MipsISA
readfile() : PseudoInst
ReadID : Ps2
readMemAtomic() : X86ISA
readMPIDR() : ArmISA
readPackedMemAtomic() : X86ISA
readRegOtherThread() : MipsISA
readSymbol() : ArmISA , X86ISA
readVecElem() : ArmISA
readVecReg : GuestABI
RealMode : X86ISA
recip_sqrt_estimate : ArmISA
recipEstimate() : ArmISA
recipSqrtEstimate() : ArmISA
red : SparcISA
reg : X86ISA
REG_AIFS : iGbReg
REG_CRCERRS : iGbReg
REG_CTRL : iGbReg
REG_CTRL_EXT : iGbReg
REG_EECD : iGbReg
REG_EERD : iGbReg
REG_EICR : iGbReg
REG_EXEC_HI : Gcn3ISA
REG_EXEC_LO : Gcn3ISA
REG_EXECZ : Gcn3ISA
REG_FCAH : iGbReg
REG_FCAL : iGbReg
REG_FCRTH : iGbReg
REG_FCRTL : iGbReg
REG_FCT : iGbReg
REG_FCTTV : iGbReg
REG_FLAT_SCRATCH_HI : Gcn3ISA
REG_FLAT_SCRATCH_LO : Gcn3ISA
REG_FWSM : iGbReg
REG_IAM : iGbReg
REG_ICR : iGbReg
REG_ICS : iGbReg
REG_IMC : iGbReg
REG_IMS : iGbReg
REG_INT_CONST_NEG_MAX : Gcn3ISA
REG_INT_CONST_NEG_MIN : Gcn3ISA
REG_INT_CONST_POS_MAX : Gcn3ISA
REG_INT_CONST_POS_MIN : Gcn3ISA
REG_ITR : iGbReg
REG_IVAR0 : iGbReg
REG_LDS_DIRECT : Gcn3ISA
REG_LEDCTL : iGbReg
REG_M0 : Gcn3ISA
REG_MANC : iGbReg
REG_MDIC : iGbReg
REG_MTA : iGbReg
REG_NEG_FOUR : Gcn3ISA
REG_NEG_HALF : Gcn3ISA
REG_NEG_ONE : Gcn3ISA
REG_NEG_TWO : Gcn3ISA
REG_PBA : iGbReg
REG_PI : Gcn3ISA
REG_POS_FOUR : Gcn3ISA
REG_POS_HALF : Gcn3ISA
REG_POS_ONE : Gcn3ISA
REG_POS_TWO : Gcn3ISA
REG_RADV : iGbReg
REG_RAH : iGbReg
REG_RAL : iGbReg
REG_RCTL : iGbReg
REG_RDBAH : iGbReg
REG_RDBAL : iGbReg
REG_RDH : iGbReg
REG_RDLEN : iGbReg
REG_RDT : iGbReg
REG_RDTR : iGbReg
REG_RESERVED_1 : Gcn3ISA
REG_RESERVED_10 : Gcn3ISA
REG_RESERVED_11 : Gcn3ISA
REG_RESERVED_12 : Gcn3ISA
REG_RESERVED_13 : Gcn3ISA
REG_RESERVED_14 : Gcn3ISA
REG_RESERVED_15 : Gcn3ISA
REG_RESERVED_16 : Gcn3ISA
REG_RESERVED_17 : Gcn3ISA
REG_RESERVED_18 : Gcn3ISA
REG_RESERVED_19 : Gcn3ISA
REG_RESERVED_2 : Gcn3ISA
REG_RESERVED_20 : Gcn3ISA
REG_RESERVED_21 : Gcn3ISA
REG_RESERVED_22 : Gcn3ISA
REG_RESERVED_23 : Gcn3ISA
REG_RESERVED_24 : Gcn3ISA
REG_RESERVED_25 : Gcn3ISA
REG_RESERVED_26 : Gcn3ISA
REG_RESERVED_27 : Gcn3ISA
REG_RESERVED_28 : Gcn3ISA
REG_RESERVED_29 : Gcn3ISA
REG_RESERVED_3 : Gcn3ISA
REG_RESERVED_30 : Gcn3ISA
REG_RESERVED_31 : Gcn3ISA
REG_RESERVED_32 : Gcn3ISA
REG_RESERVED_4 : Gcn3ISA
REG_RESERVED_5 : Gcn3ISA
REG_RESERVED_6 : Gcn3ISA
REG_RESERVED_7 : Gcn3ISA
REG_RESERVED_8 : Gcn3ISA
REG_RESERVED_9 : Gcn3ISA
REG_RFCTL : iGbReg
REG_RLPML : iGbReg
REG_RXCSUM : iGbReg
REG_RXDCTL : iGbReg
REG_SCC : Gcn3ISA
REG_SGPR_MAX : Gcn3ISA
REG_SGPR_MIN : Gcn3ISA
REG_SRC_DPP : Gcn3ISA
REG_SRC_LITERAL : Gcn3ISA
REG_SRC_SWDA : Gcn3ISA
REG_SRRCTL : iGbReg
REG_STATUS : iGbReg
REG_SWFWSYNC : iGbReg
REG_SWSM : iGbReg
REG_TADV : iGbReg
REG_TBA_HI : Gcn3ISA
REG_TBA_LO : Gcn3ISA
REG_TCTL : iGbReg
REG_TDBAH : iGbReg
REG_TDBAL : iGbReg
REG_TDH : iGbReg
REG_TDLEN : iGbReg
REG_TDT : iGbReg
REG_TDWBAH : iGbReg
REG_TDWBAL : iGbReg
REG_TIDV : iGbReg
REG_TIPG : iGbReg
REG_TMA_HI : Gcn3ISA
REG_TMA_LO : Gcn3ISA
REG_TTMP_0 : Gcn3ISA
REG_TTMP_1 : Gcn3ISA
REG_TTMP_10 : Gcn3ISA
REG_TTMP_11 : Gcn3ISA
REG_TTMP_2 : Gcn3ISA
REG_TTMP_3 : Gcn3ISA
REG_TTMP_4 : Gcn3ISA
REG_TTMP_5 : Gcn3ISA
REG_TTMP_6 : Gcn3ISA
REG_TTMP_7 : Gcn3ISA
REG_TTMP_8 : Gcn3ISA
REG_TTMP_9 : Gcn3ISA
REG_TXDCA_CTL : iGbReg
REG_TXDCTL : iGbReg
REG_VCC_HI : Gcn3ISA
REG_VCC_LO : Gcn3ISA
REG_VCCZ : Gcn3ISA
REG_VET : iGbReg
REG_VFTA : iGbReg
REG_VGPR_MAX : Gcn3ISA
REG_VGPR_MIN : Gcn3ISA
REG_WUC : iGbReg
REG_WUFC : iGbReg
REG_WUS : iGbReg
REG_XNACK_MASK_HI : Gcn3ISA
REG_XNACK_MASK_LO : Gcn3ISA
REG_ZERO : Gcn3ISA
RegContextParam : ArmISA
RegContextVal : ArmISA
regInfo() : Sinic
registerDumpCallback() : Stats
registerHandlers() : Stats
registerName() : RiscvISA
registerPythonStatsHandlers() : Stats
registerResetCallback() : Stats
regList : ArmISA
regValid() : Sinic
remainder : sc_dt
RemoteMode : Ps2::Mouse
Rep : X86ISA
rep : X86ISA
repne : X86ISA
Repne : X86ISA
reportCatchActions : sc_gem5
reportForcedActions : sc_gem5
reportHandlerProc : sc_gem5
reportIdToMsgMap() : sc_gem5
reportifyException() : sc_gem5
reportMsgInfoMap() : sc_gem5
reportSeverityNames : sc_gem5
reportSevInfos : sc_gem5
reportSuppressedActions : sc_gem5
reportVerbosityLevel : sc_gem5
reportWarningsAsErrors : sc_gem5
res1_13_12_el2 : ArmISA
res1_7_0_el2 : ArmISA
res1_8_el2 : ArmISA
res1_9_el2 : ArmISA
Resend : Ps2
reserved_20_13 : ArmISA
reserved_22 : ArmISA
reserved_30_26 : ArmISA
reserved_4_3 : ArmISA
Reset : Ps2
reset() : Stats , UnitTest
resetException : sc_gem5
resetHandler : Stats
resetQueue : Stats
resetstats() : PseudoInst
ResetWrapMode : Ps2::Mouse
resolve() : Stats
restoreThread() : MipsISA
Result : Stats
ReturnAddressReg : ArmISA , MipsISA , SparcISA , X86ISA
ReturnAddrReg : RiscvISA
ReturnValueReg : ArmISA , MipsISA , PowerISA , RiscvISA , SparcISA , X86ISA
ReturnValueReg1 : ArmISA
ReturnValueReg2 : ArmISA
ReturnValueRegs : RiscvISA
rev : MipsISA , RiscvISA
reverse() : sc_dt
RexPrefix : X86ISA
rf : X86ISA
RFBit : X86ISA
RFLAGBit : X86ISA
rfr : ArmISA
rightButton : Ps2
rInit : X86ISA
ripl : MipsISA , RiscvISA
Riscv32 : Loader
Riscv64 : Loader
rm : ArmISA , X86ISA
rMode : ArmISA
rn : ArmISA , PowerISA
RN : X86ISA
RND_DOWN : ArmISA , MipsISA
RND_NEAREST : ArmISA , MipsISA
RND_UP : ArmISA , MipsISA
RND_ZERO : ArmISA , MipsISA
rndr : ArmISA
rnst : MipsISA
ROR : ArmISA
rotate : ArmISA
rotate_imm() : ArmISA
ROUND : MipsISA
roundFP() : MipsISA
roundingModes : ArmISA
RoundMode : ArmISA , MipsISA
roundNearestEven() : Gcn3ISA
roundNEven() : ArmISA
roundPage() : ArmISA
RoundPage() : MipsISA
rpl : X86ISA
rpns() : PseudoInst
rr : ArmISA
rrotate() : sc_dt
rs : ArmISA , iGbReg::TxdOp , PowerISA
rsh_scfx_rep() : sc_dt
rshift() : sc_dt
rsmCycle : X86ISA
rsvd : ArmISA
rt : ArmISA
rw : ArmISA
rw0 : X86ISA
rw1 : X86ISA
rw2 : X86ISA
rw3 : X86ISA
RX : X86ISA
RXDE_CE : iGbReg
RXDE_IPE : iGbReg
RXDE_RXE : iGbReg
RXDE_SE : iGbReg
RXDE_SEQ : iGbReg
RXDE_TCPE : iGbReg
RXDEE_CE : iGbReg
RXDEE_HBO : iGbReg
RXDEE_IPE : iGbReg
RXDEE_LE : iGbReg
RXDEE_OSE : iGbReg
RXDEE_PE : iGbReg
RXDEE_TCPE : iGbReg
RXDEE_USE : iGbReg
RXDP_IPV4 : iGbReg
RXDP_IPV4E : iGbReg
RXDP_IPV6 : iGbReg
RXDP_IPV6E : iGbReg
RXDP_NFS : iGbReg
RXDP_SCTP : iGbReg
RXDP_TCP : iGbReg
RXDP_UDP : iGbReg
RXDS_CRCV : iGbReg
RXDS_DD : iGbReg
RXDS_DYNINT : iGbReg
RXDS_EOP : iGbReg
RXDS_IPCS : iGbReg
RXDS_IXSM : iGbReg
RXDS_PIF : iGbReg
RXDS_TCPCS : iGbReg
RXDS_UDPCS : iGbReg
RXDS_UDPV : iGbReg
RXDS_VP : iGbReg
RXDT_ADV_ONEBUF : iGbReg
RXDT_ADV_SPLIT_A : iGbReg
RXDT_LEGACY : iGbReg
RxStateStrings : Sinic