gem5  v20.1.0.0
pseudo_inst.cc
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1 /*
2  * Copyright (c) 2014 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
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8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
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14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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27  */
28 
29 #include "arch/x86/pseudo_inst.hh"
30 
31 #include "arch/x86/fs_workload.hh"
32 #include "arch/x86/isa_traits.hh"
33 #include "cpu/thread_context.hh"
34 #include "debug/PseudoInst.hh"
36 #include "sim/process.hh"
37 
38 using namespace X86ISA;
39 
40 namespace X86ISA {
41 
42 /*
43  * This function is executed when the simulation is executing the pagefault
44  * handler in System Emulation mode.
45  */
46 void
48 {
49  DPRINTF(PseudoInst, "PseudoInst::m5PageFault()\n");
50 
51  Process *p = tc->getProcessPtr();
52  if (!p->fixupFault(tc->readMiscReg(MISCREG_CR2))) {
53  PortProxy &proxy = tc->getVirtProxy();
54  // at this point we should have 6 values on the interrupt stack
55  int size = 6;
56  uint64_t is[size];
57  // reading the interrupt handler stack
58  proxy.readBlob(ISTVirtAddr + PageBytes - size * sizeof(uint64_t),
59  &is, sizeof(is));
60  panic("Page fault at addr %#x\n\tInterrupt handler stack:\n"
61  "\tss: %#x\n"
62  "\trsp: %#x\n"
63  "\trflags: %#x\n"
64  "\tcs: %#x\n"
65  "\trip: %#x\n"
66  "\terr_code: %#x\n",
68  is[5], is[4], is[3], is[2], is[1], is[0]);
69  }
70 }
71 
72 } // namespace X86ISA
pseudo_inst.hh
Process
Definition: process.hh:65
X86ISA::MISCREG_CR2
@ MISCREG_CR2
Definition: misc.hh:107
ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
MipsISA::is
Bitfield< 24, 22 > is
Definition: pra_constants.hh:232
PseudoInst
Definition: pseudo_inst.cc:76
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
process.hh
X86ISA::PageBytes
const Addr PageBytes
Definition: isa_traits.hh:48
isa_traits.hh
X86ISA
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
X86ISA::m5PageFault
void m5PageFault(ThreadContext *tc)
Definition: pseudo_inst.cc:47
ThreadContext::getVirtProxy
virtual PortProxy & getVirtProxy()=0
PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:80
X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
X86ISA::ISTVirtAddr
const Addr ISTVirtAddr
Definition: fs_workload.hh:74
se_translating_port_proxy.hh
fs_workload.hh
PortProxy::readBlob
void readBlob(Addr addr, void *p, int size) const
Higher level interfaces based on the above.
Definition: port_proxy.hh:177
thread_context.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171

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