gem5  v20.1.0.0
display.h
Go to the documentation of this file.
1 /*****************************************************************************
2 
3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4  more contributor license agreements. See the NOTICE file distributed
5  with this work for additional information regarding copyright ownership.
6  Accellera licenses this file to you under the Apache License, Version 2.0
7  (the "License"); you may not use this file except in compliance with the
8  License. You may obtain a copy of the License at
9 
10  http://www.apache.org/licenses/LICENSE-2.0
11 
12  Unless required by applicable law or agreed to in writing, software
13  distributed under the License is distributed on an "AS IS" BASIS,
14  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15  implied. See the License for the specific language governing
16  permissions and limitations under the License.
17 
18  *****************************************************************************/
19 
20 /*****************************************************************************
21 
22  display.h --
23 
24  Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 
39 #include "common.h"
40 
42 {
44 
45  sc_in_clk clk;
46 
47  const sc_signal<int>& in_data1; // Input port
48  const sc_signal_bool_vector4& in_data2; // Input port
49  const sc_signal_bool_vector4& in_data3; // Input port
50  const sc_signal_bool_vector8& in_data4; // Input port
51  const sc_signal_bool_vector8& in_data5; // Input port
52  const sc_signal<bool>& in_valid;
53 
54  display( sc_module_name NAME,
55  sc_clock& CLK,
56  const sc_signal<int>& IN_DATA1,
57  const sc_signal_bool_vector4& IN_DATA2,
58  const sc_signal_bool_vector4& IN_DATA3,
59  const sc_signal_bool_vector8& IN_DATA4,
60  const sc_signal_bool_vector8& IN_DATA5,
61  const sc_signal<bool>& IN_VALID
62  )
63  :
64  in_data1(IN_DATA1),
65  in_data2(IN_DATA2),
66  in_data3(IN_DATA3),
67  in_data4(IN_DATA4),
68  in_data5(IN_DATA5),
69  in_valid(IN_VALID)
70  {
71  clk(CLK);
72  SC_CTHREAD( entry, clk.pos() );
73  }
74 
75  void entry();
76 };
77 
78 // EOF
sc_signal_bool_vector4
sc_signal< sc_bv< 4 > > sc_signal_bool_vector4
Definition: common.h:43
sc_signal_bool_vector8
sc_signal< sc_bv< 8 > > sc_signal_bool_vector8
Definition: common.h:44
Stats::display
const FlagsType display
Print this stat.
Definition: info.hh:47
common.h
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
SC_MODULE
SC_MODULE(display)
Definition: display.h:40
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319

Generated on Wed Sep 30 2020 14:02:17 for gem5 by doxygen 1.8.17