gem5
v20.1.0.0
systemc
tests
systemc
misc
cae_test
general
arith
modulo
display.h
Go to the documentation of this file.
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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display.h --
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Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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#include "
common.h
"
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SC_MODULE
(
display
)
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{
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SC_HAS_PROCESS
(
display
);
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sc_in_clk
clk;
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const
sc_signal<int>& in_data1;
// Input port
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const
sc_signal_bool_vector4
& in_data2;
// Input port
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const
sc_signal_bool_vector4
& in_data3;
// Input port
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const
sc_signal_bool_vector8
& in_data4;
// Input port
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const
sc_signal_bool_vector8
& in_data5;
// Input port
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const
sc_signal<bool>& in_valid;
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display
( sc_module_name NAME,
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sc_clock& CLK,
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const
sc_signal<int>& IN_DATA1,
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const
sc_signal_bool_vector4
& IN_DATA2,
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const
sc_signal_bool_vector4
& IN_DATA3,
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const
sc_signal_bool_vector8
& IN_DATA4,
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const
sc_signal_bool_vector8
& IN_DATA5,
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const
sc_signal<bool>& IN_VALID
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)
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:
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in_data1(IN_DATA1),
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in_data2(IN_DATA2),
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in_data3(IN_DATA3),
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in_data4(IN_DATA4),
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in_data5(IN_DATA5),
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in_valid(IN_VALID)
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{
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clk(CLK);
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SC_CTHREAD
( entry, clk.pos() );
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}
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void
entry();
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};
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// EOF
sc_signal_bool_vector4
sc_signal< sc_bv< 4 > > sc_signal_bool_vector4
Definition:
common.h:43
sc_signal_bool_vector8
sc_signal< sc_bv< 8 > > sc_signal_bool_vector8
Definition:
common.h:44
Stats::display
const FlagsType display
Print this stat.
Definition:
info.hh:47
common.h
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition:
sc_clock.hh:116
SC_MODULE
SC_MODULE(display)
Definition:
display.h:40
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition:
sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition:
sc_module.hh:319
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