gem5
v20.1.0.0
systemc
tests
systemc
misc
cae_test
general
arith
subtract
bitwidth
stimulus.h
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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*****************************************************************************/
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/*****************************************************************************
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stimulus.h --
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Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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#include "
common.h
"
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SC_MODULE
( stimulus )
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{
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SC_HAS_PROCESS
( stimulus );
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sc_in_clk
clk;
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sc_signal<bool>&
reset
;
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sc_signal_bool_vector2
& out_value1;
// Output port
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sc_signal_bool_vector4
& out_value2;
// Output port
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sc_signal_bool_vector6
& out_value3;
// Output port
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sc_signal_bool_vector8
& out_value4;
// Output port
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sc_signal<bool>& out_valid;
// Output port
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const
sc_signal<bool>& in_ack;
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//
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// Constructor
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//
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stimulus(
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sc_module_name NAME,
// reference name
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sc_clock& CLK,
// clock
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sc_signal<bool>& RESET,
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sc_signal_bool_vector2
& OUT_VALUE1,
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sc_signal_bool_vector4
& OUT_VALUE2,
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sc_signal_bool_vector6
& OUT_VALUE3,
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sc_signal_bool_vector8
& OUT_VALUE4,
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sc_signal<bool>& OUT_VALID,
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const
sc_signal<bool>& IN_ACK
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)
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:
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reset
(RESET),
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out_value1 (OUT_VALUE1),
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out_value2 (OUT_VALUE2),
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out_value3 (OUT_VALUE3),
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out_value4 (OUT_VALUE4),
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out_valid (OUT_VALID),
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in_ack (IN_ACK)
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{
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clk (CLK);
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SC_CTHREAD
( entry, clk.pos() );
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};
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void
entry();
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};
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// EOF
sc_signal_bool_vector4
sc_signal< sc_bv< 4 > > sc_signal_bool_vector4
Definition:
common.h:43
sc_signal_bool_vector8
sc_signal< sc_bv< 8 > > sc_signal_bool_vector8
Definition:
common.h:44
sc_signal_bool_vector2
sc_signal< sc_bv< 2 > > sc_signal_bool_vector2
Definition:
common.h:43
Stats::reset
void reset()
Definition:
statistics.cc:569
SC_MODULE
SC_MODULE(stimulus)
Definition:
stimulus.h:40
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition:
sc_clock.hh:116
sc_signal_bool_vector6
sc_signal< sc_bv< 6 > > sc_signal_bool_vector6
Definition:
common.h:44
common.h
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition:
sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition:
sc_module.hh:319
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