gem5
v20.1.0.0
systemc
tests
systemc
misc
user_guide
chpt4.2
stage1.h
Go to the documentation of this file.
1
/*****************************************************************************
2
3
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4
more contributor license agreements. See the NOTICE file distributed
5
with this work for additional information regarding copyright ownership.
6
Accellera licenses this file to you under the Apache License, Version 2.0
7
(the "License"); you may not use this file except in compliance with the
8
License. You may obtain a copy of the License at
9
10
http://www.apache.org/licenses/LICENSE-2.0
11
12
Unless required by applicable law or agreed to in writing, software
13
distributed under the License is distributed on an "AS IS" BASIS,
14
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15
implied. See the License for the specific language governing
16
permissions and limitations under the License.
17
18
*****************************************************************************/
19
20
/*****************************************************************************
21
22
stage1.h --
23
24
Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26
*****************************************************************************/
27
28
/*****************************************************************************
29
30
MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31
changes you are making here.
32
33
Name, Affiliation, Date:
34
Description of Modification:
35
36
*****************************************************************************/
37
38
/* Filename stage1.h */
39
/* This is the interface file for synchronous process `stage1' */
40
41
#include "systemc.h"
42
43
SC_MODULE
( stage1 )
44
{
45
SC_HAS_PROCESS
( stage1 );
46
47
sc_in_clk
clk;
48
49
const
sc_signal<double>& in1;
//input
50
const
sc_signal<double>& in2;
//input
51
sc_signal<double>&
sum
;
//output
52
sc_signal<double>& diff;
//output
53
54
//Constructor
55
stage1(sc_module_name NAME,
56
sc_clock& CLK,
57
const
sc_signal<double>& IN1,
58
const
sc_signal<double>& IN2,
59
sc_signal<double>& SUM,
60
sc_signal<double>& DIFF)
61
: in1(IN1), in2(IN2),
sum
(SUM), diff(DIFF)
62
{
63
clk(CLK);
64
SC_CTHREAD
( entry, clk.pos() );
65
}
66
67
// Process functionality in member function below
68
void
entry();
69
};
70
71
RiscvISA::sum
Bitfield< 18 > sum
Definition:
registers.hh:609
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition:
sc_clock.hh:116
SC_MODULE
SC_MODULE(stage1)
Definition:
stage1.h:43
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition:
sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition:
sc_module.hh:319
Generated on Wed Sep 30 2020 14:02:18 for gem5 by
doxygen
1.8.17