gem5  v20.1.0.0
ArmISA::SupervisorCall Member List

This is the complete list of members for ArmISA::SupervisorCall, including all inherited members.

aarch64FaultSourcesArmISA::ArmFaultstatic
abortDisable(ThreadContext *tc) overrideArmISA::ArmFaultVals< SupervisorCall >inlinevirtual
AccessFlagLL enum valueArmISA::ArmFault
AddressSizeLL enum valueArmISA::ArmFault
AlignmentFault enum valueArmISA::ArmFault
annotate(AnnotationIDs id, uint64_t val)ArmISA::ArmFaultinlinevirtual
AnnotationIDs enum nameArmISA::ArmFault
AR enum valueArmISA::ArmFault
ArmFault(ExtMachInst _machInst=0, uint32_t _iss=0)ArmISA::ArmFaultinline
ArmFaultVals(ExtMachInst _machInst=0, uint32_t _iss=0)ArmISA::ArmFaultVals< SupervisorCall >inline
armPcElrOffset() overrideArmISA::ArmFaultVals< SupervisorCall >inlinevirtual
armPcOffset(bool isHyp) overrideArmISA::ArmFaultVals< SupervisorCall >inlinevirtual
AsynchPtyErrOnMemoryAccess enum valueArmISA::ArmFault
AsynchronousExternalAbort enum valueArmISA::ArmFault
BRKPOINT enum valueArmISA::ArmFault
bStepArmISA::ArmFaultprotected
CM enum valueArmISA::ArmFault
countStat() overrideArmISA::ArmFaultVals< SupervisorCall >inlinevirtual
DebugEvent enum valueArmISA::ArmFault
DebugType enum nameArmISA::ArmFault
DomainLL enum valueArmISA::ArmFault
ec(ThreadContext *tc) const overrideArmISA::SupervisorCallvirtual
FaultSource enum nameArmISA::ArmFault
FaultSourceInvalid enum valueArmISA::ArmFault
faultUpdatedArmISA::ArmFaultprotected
fiqDisable(ThreadContext *tc) overrideArmISA::ArmFaultVals< SupervisorCall >inlinevirtual
from64ArmISA::ArmFaultprotected
fromELArmISA::ArmFaultprotected
fromModeArmISA::ArmFaultprotected
getFaultAddrReg64() constArmISA::ArmFault
getFaultVAddr(Addr &va) constArmISA::ArmFaultinlinevirtual
getFsr(ThreadContext *tc) constArmISA::ArmFaultinlinevirtual
getSyndromeReg64() constArmISA::ArmFault
getToMode() constArmISA::ArmFaultinline
getVector(ThreadContext *tc)ArmISA::ArmFaultprotectedvirtual
getVector64(ThreadContext *tc)ArmISA::ArmFaultprotected
hypRoutedArmISA::ArmFaultprotected
instrAnnotate(const StaticInstPtr &inst)ArmISA::ArmFault
InstructionCacheMaintenance enum valueArmISA::ArmFault
invoke(ThreadContext *tc, const StaticInstPtr &inst=StaticInst::nullStaticInstPtr) overrideArmISA::SupervisorCallvirtual
invoke64(ThreadContext *tc, const StaticInstPtr &inst=StaticInst::nullStaticInstPtr)ArmISA::ArmFault
isResetSPSR()ArmISA::ArmFaultinline
iss() const overrideArmISA::SupervisorCallvirtual
ArmFaultVals< SupervisorCall >::iss() const overrideArmISA::ArmFaultVals< SupervisorCall >inline
issRawArmISA::ArmFaultprotected
isStage2() constArmISA::ArmFaultinlinevirtual
longDescFaultSourcesArmISA::ArmFaultstatic
LpaeTran enum valueArmISA::ArmFault
machInstArmISA::ArmFaultprotected
name() const overrideArmISA::ArmFaultVals< SupervisorCall >inline
ArmISA::ArmFault::name() const =0FaultBasepure virtual
nextMode() overrideArmISA::ArmFaultVals< SupervisorCall >inlinevirtual
NODEBUG enum valueArmISA::ArmFault
NumFaultSources enum valueArmISA::ArmFault
OFA enum valueArmISA::ArmFault
offset(ThreadContext *tc) overrideArmISA::ArmFaultVals< SupervisorCall >virtual
offset64(ThreadContext *tc) overrideArmISA::ArmFaultVals< SupervisorCall >virtual
OVA enum valueArmISA::ArmFault
overrideEcArmISA::SupervisorCallprotected
PermissionLL enum valueArmISA::ArmFault
PrefetchTLBMiss enum valueArmISA::ArmFault
PrefetchUncacheable enum valueArmISA::ArmFault
routeToHyp(ThreadContext *tc) const overrideArmISA::SupervisorCallvirtual
routeToMonitor(ThreadContext *tc) const overrideArmISA::ArmFaultVals< SupervisorCall >inlinevirtual
S1PTW enum valueArmISA::ArmFault
SAS enum valueArmISA::ArmFault
setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)ArmISA::ArmFaultvirtual
SF enum valueArmISA::ArmFault
shortDescFaultSourcesArmISA::ArmFaultstatic
spanArmISA::ArmFaultprotected
SRT enum valueArmISA::ArmFault
SSE enum valueArmISA::ArmFault
SupervisorCall(ExtMachInst _machInst, uint32_t _iss, ExceptionClass _overrideEc=EC_INVALID)ArmISA::SupervisorCallinline
SynchExtAbtOnTranslTableWalkLL enum valueArmISA::ArmFault
SynchPtyErrOnMemoryAccess enum valueArmISA::ArmFault
SynchPtyErrOnTranslTableWalkLL enum valueArmISA::ArmFault
SynchronousExternalAbort enum valueArmISA::ArmFault
thumbPcElrOffset() overrideArmISA::ArmFaultVals< SupervisorCall >inlinevirtual
thumbPcOffset(bool isHyp) overrideArmISA::ArmFaultVals< SupervisorCall >inlinevirtual
TLBConflictAbort enum valueArmISA::ArmFault
to64ArmISA::ArmFaultprotected
toELArmISA::ArmFaultprotected
toModeArmISA::ArmFaultprotected
TranMethod enum nameArmISA::ArmFault
TranslationLL enum valueArmISA::ArmFault
UnknownTran enum valueArmISA::ArmFault
update(ThreadContext *tc)ArmISA::ArmFault
valsArmISA::ArmFaultVals< SupervisorCall >protectedstatic
vals("Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 0, 0, 0, 0, false, true, true, EC_UNKNOWN)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 4, 2, 0, 0, true, false, false, EC_UNKNOWN)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON, 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 4, 4, 4, 4, true, false, false, EC_HVC)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 8, 8, 0, 0, true, true, false, EC_INVALID)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 0, 0, 0, 0, false, false, false, EC_UNKNOWN)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON, 4, 2, 0, 0, false, false, false, EC_UNKNOWN)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 4, 4, 0, 0, false, true, false, EC_UNKNOWN)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 4, 4, 0, 0, false, true, false, EC_INVALID)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 4, 4, 0, 0, false, true, true, EC_UNKNOWN)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 4, 4, 0, 0, false, true, true, EC_INVALID)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Illegal Inst Set State Fault", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, false, false, false, EC_UNKNOWN)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 0, 0, 0, 0, false, true, true, EC_SERROR)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Hardware Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_HW_BREAKPOINT)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("Watchpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_WATCHPOINT)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("SoftwareStep", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, EC_SOFTWARE_STEP)ArmISA::ArmFaultVals< SupervisorCall >protected
vals("ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 0, 0, 0, 0, false, true, true, EC_UNKNOWN)ArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
valsArmISA::ArmFaultVals< SupervisorCall >protected
VECTORCATCH enum valueArmISA::ArmFault
vectorCatch(ThreadContext *tc, const StaticInstPtr &inst)ArmISA::ArmFault
vectorCatchFlag() const overrideArmISA::SupervisorCallinlinevirtual
VmsaTran enum valueArmISA::ArmFault
WPOINT_CM enum valueArmISA::ArmFault
WPOINT_NOCM enum valueArmISA::ArmFault
~FaultBase()FaultBaseinlinevirtual

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