gem5  v20.1.0.0
Gicv3CPUInterface Member List

This is the complete list of members for Gicv3CPUInterface, including all inherited members.

A3VGicv3CPUInterfaceprotected
A3VGicv3CPUInterfaceprotected
assertWakeRequest(void)Gicv3CPUInterfaceprotected
BaseISADevice()ArmISA::BaseISADevice
BitUnion32(ICH_LRC) Bitfield< 31Gicv3CPUInterfaceprotected
BitUnion64(ICC_CTLR_EL1) Bitfield< 63Gicv3CPUInterfaceprotected
BitUnion64(ICH_HCR_EL2) Bitfield< 63Gicv3CPUInterfaceprotected
bpr1(Gicv3::GroupId group)Gicv3CPUInterfaceprotected
CBPRGicv3CPUInterfaceprotected
CBPR_EL1NSGicv3CPUInterfaceprotected
CBPR_EL1SGicv3CPUInterfaceprotected
clearPendingInterrupts(void)Gicv3CPUInterfaceprotected
cpuIdGicv3CPUInterfaceprotected
currEL() constGicv3CPUInterfaceprotected
currentSection()Serializablestatic
deactivateIRQ(uint32_t intid, Gicv3::GroupId group)Gicv3CPUInterfaceprotected
deassertWakeRequest(void)Gicv3CPUInterfaceprotected
DFBGicv3CPUInterfaceprotected
DIBGicv3CPUInterfaceprotected
distributorGicv3CPUInterfaceprotected
dropPriority(Gicv3::GroupId group)Gicv3CPUInterfaceprotected
EnGicv3CPUInterfaceprotected
EnableGicv3CPUInterfaceprotected
EnableGicv3CPUInterfaceprotected
EnableGrp1NSGicv3CPUInterfaceprotected
EnableGrp1SGicv3CPUInterfaceprotected
EndBitUnion(ICC_CTLR_EL1) BitUnion64(ICC_CTLR_EL3) Bitfield< 63Gicv3CPUInterfaceprotected
EndBitUnion(ICC_CTLR_EL3) BitUnion64(ICC_IGRPEN0_EL1) Bitfield< 63Gicv3CPUInterfaceprotected
EndBitUnion(ICC_IGRPEN0_EL1) BitUnion64(ICC_IGRPEN1_EL1) Bitfield< 63Gicv3CPUInterfaceprotected
EndBitUnion(ICC_IGRPEN1_EL1) BitUnion64(ICC_IGRPEN1_EL3) Bitfield< 63Gicv3CPUInterfaceprotected
EndBitUnion(ICC_IGRPEN1_EL3) BitUnion64(ICC_SRE_EL1) Bitfield< 63Gicv3CPUInterfaceprotected
EndBitUnion(ICC_SRE_EL1) BitUnion64(ICC_SRE_EL2) Bitfield< 63Gicv3CPUInterfaceprotected
EndBitUnion(ICC_SRE_EL2) BitUnion64(ICC_SRE_EL3) Bitfield< 63Gicv3CPUInterfaceprotected
EndBitUnion(ICC_SRE_EL3) static const uint8_t PRIORITY_BITSGicv3CPUInterfaceprotected
EndBitUnion(ICH_HCR_EL2) BitUnion64(ICH_LR_EL2) Bitfield< 63Gicv3CPUInterfaceprotected
EndBitUnion(ICH_LR_EL2) static const uint64_t ICH_LR_EL2_STATE_INVALID=0Gicv3CPUInterfaceprotectedpure virtual
EndBitUnion(ICH_LRC) BitUnion64(ICH_MISR_EL2) Bitfield< 63Gicv3CPUInterfaceprotected
EndBitUnion(ICH_MISR_EL2) BitUnion64(ICH_VMCR_EL2) Bitfield< 63Gicv3CPUInterfaceprotected
EndBitUnion(ICH_VMCR_EL2) BitUnion64(ICH_VTR_EL2) Bitfield< 63Gicv3CPUInterfaceprotected
EndBitUnion(ICH_VTR_EL2) BitUnion64(ICV_CTLR_EL1) Bitfield< 63Gicv3CPUInterfaceprotected
EOIGicv3CPUInterfaceprotected
EOIGicv3CPUInterfaceprotected
EOIGicv3CPUInterfaceprotected
EOIcountGicv3CPUInterfaceprotected
eoiMaintenanceInterruptStatus() constGicv3CPUInterfaceprotected
EOImodeGicv3CPUInterfaceprotected
EOImode_EL1NSGicv3CPUInterfaceprotected
EOImode_EL1SGicv3CPUInterfaceprotected
EOImode_EL3Gicv3CPUInterfaceprotected
ExtRangeGicv3CPUInterfaceprotected
generateSGI(RegVal val, Gicv3::GroupId group)Gicv3CPUInterfaceprotected
getHCREL2FMO() constGicv3CPUInterfaceprotected
getHCREL2IMO() constGicv3CPUInterfaceprotected
getHPPIR0() constGicv3CPUInterfaceprotected
getHPPIR1() constGicv3CPUInterfaceprotected
getHPPVILR() constGicv3CPUInterfaceprotected
gicGicv3CPUInterfaceprotected
GIC_MIN_BPRGicv3CPUInterfaceprotectedstatic
GIC_MIN_BPR_NSGicv3CPUInterfaceprotectedstatic
GIC_MIN_VBPRGicv3CPUInterfaceprotectedstatic
GICC_ABPR enum valueGicv3CPUInterfaceprotected
GICC_AEOIR enum valueGicv3CPUInterfaceprotected
GICC_AHPPIR enum valueGicv3CPUInterfaceprotected
GICC_AIAR enum valueGicv3CPUInterfaceprotected
GICC_APRGicv3CPUInterfaceprotectedstatic
GICC_BPR enum valueGicv3CPUInterfaceprotected
GICC_CTLR enum valueGicv3CPUInterfaceprotected
GICC_EOIR enum valueGicv3CPUInterfaceprotected
GICC_HPPI enum valueGicv3CPUInterfaceprotected
GICC_IAR enum valueGicv3CPUInterfaceprotected
GICC_IIDR enum valueGicv3CPUInterfaceprotected
GICC_NSAPRGicv3CPUInterfaceprotectedstatic
GICC_PMR enum valueGicv3CPUInterfaceprotected
GICC_RPR enum valueGicv3CPUInterfaceprotected
GICC_STATUSR enum valueGicv3CPUInterfaceprotected
GICH_APRGicv3CPUInterfaceprotectedstatic
GICH_EISR enum valueGicv3CPUInterfaceprotected
GICH_ELRSR enum valueGicv3CPUInterfaceprotected
GICH_HCR enum valueGicv3CPUInterfaceprotected
GICH_LRGicv3CPUInterfaceprotectedstatic
GICH_MISR enum valueGicv3CPUInterfaceprotected
GICH_VMCR enum valueGicv3CPUInterfaceprotected
GICH_VTR enum valueGicv3CPUInterfaceprotected
Gicv3CPUInterface(Gicv3 *gic, uint32_t cpu_id)Gicv3CPUInterface
Gicv3Distributor classGicv3CPUInterfacefriend
Gicv3Redistributor classGicv3CPUInterfacefriend
GroupGicv3CPUInterfaceprotected
GroupGicv3CPUInterfaceprotected
groupEnabled(Gicv3::GroupId group) constGicv3CPUInterfaceprotected
groupPriorityMask(Gicv3::GroupId group)Gicv3CPUInterfaceprotected
haveEL(ArmISA::ExceptionLevel el) constGicv3CPUInterfaceprotected
havePendingInterrupts(void) constGicv3CPUInterfaceprotected
highestActiveGroup() constGicv3CPUInterfaceprotected
highestActivePriority() constGicv3CPUInterfaceprotected
hppiGicv3CPUInterfaceprotected
hppiCanPreempt()Gicv3CPUInterfaceprotected
hppviCanPreempt(int lrIdx) constGicv3CPUInterfaceprotected
HWGicv3CPUInterfaceprotected
HWGicv3CPUInterfaceprotected
ICH_LR_EL2_STATE_ACTIVEGicv3CPUInterfaceprotectedstatic
ICH_LR_EL2_STATE_ACTIVE_PENDINGGicv3CPUInterfaceprotectedstatic
ICH_LR_EL2_STATE_PENDINGGicv3CPUInterfaceprotectedstatic
IDbitsGicv3CPUInterfaceprotected
IDbitsGicv3CPUInterfaceprotected
init()Gicv3CPUInterface
inSecureState() constGicv3CPUInterfaceprotected
intSignalType(Gicv3::GroupId group) constGicv3CPUInterfaceprotected
isaArmISA::BaseISADeviceprotected
isAA64() constGicv3CPUInterfaceprotected
isEL3OrMon() constGicv3CPUInterfaceprotected
isEOISplitMode() constGicv3CPUInterfaceprotected
isSecureBelowEL3() constGicv3CPUInterfaceprotected
ListRegsGicv3CPUInterfaceprotected
LRENPGicv3CPUInterfaceprotected
LRENPIEGicv3CPUInterfaceprotected
maintenanceInterruptGicv3CPUInterfaceprotected
maintenanceInterruptStatus() constGicv3CPUInterfaceprotected
nDSGicv3CPUInterfaceprotected
NPGicv3CPUInterfaceprotected
NPIEGicv3CPUInterfaceprotected
pathSerializableprivatestatic
pINTIDGicv3CPUInterfaceprotected
pINTIDGicv3CPUInterfaceprotected
PMHEGicv3CPUInterfaceprotected
PREbitsGicv3CPUInterfaceprotected
PRIbitsGicv3CPUInterfaceprotected
PRIbitsGicv3CPUInterfaceprotected
PriorityGicv3CPUInterfaceprotected
PriorityGicv3CPUInterfaceprotected
readBankedMiscReg(ArmISA::MiscRegIndex misc_reg) constGicv3CPUInterfaceprotected
readMiscReg(int misc_reg) overrideGicv3CPUInterfacevirtual
redistributorGicv3CPUInterfaceprotected
res0Gicv3CPUInterfaceprotected
res0_0Gicv3CPUInterfaceprotected
res0_0Gicv3CPUInterfaceprotected
res0_0Gicv3CPUInterfaceprotected
res0_0Gicv3CPUInterfaceprotected
res0_0Gicv3CPUInterfaceprotected
res0_0Gicv3CPUInterfaceprotected
res0_0Gicv3CPUInterfaceprotected
res0_0Gicv3CPUInterfaceprotected
res0_1Gicv3CPUInterfaceprotected
res0_1Gicv3CPUInterfaceprotected
res0_1Gicv3CPUInterfaceprotected
res0_1Gicv3CPUInterfaceprotected
res0_1Gicv3CPUInterfaceprotected
res0_1Gicv3CPUInterfaceprotected
res0_1Gicv3CPUInterfaceprotected
res0_1Gicv3CPUInterfaceprotected
res0_2Gicv3CPUInterfaceprotected
res0_2Gicv3CPUInterfaceprotected
res0_3Gicv3CPUInterfaceprotected
res1Gicv3CPUInterfaceprotected
resetHppi(uint32_t intid)Gicv3CPUInterfaceprotected
RMGicv3CPUInterfaceprotected
RSSGicv3CPUInterfaceprotected
SEISGicv3CPUInterfaceprotected
SEISGicv3CPUInterfaceprotected
Serializable()Serializable
serialize(CheckpointOut &cp) const overrideGicv3CPUInterfaceprotectedvirtual
serializeAll(const std::string &cpt_dir)Serializablestatic
serializeSection(CheckpointOut &cp, const char *name) constSerializable
serializeSection(CheckpointOut &cp, const std::string &name) constSerializableinline
setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) constGicv3CPUInterfaceprotected
setISA(ISA *isa)ArmISA::BaseISADevicevirtual
setMiscReg(int misc_reg, RegVal val) overrideGicv3CPUInterfacevirtual
setThreadContext(ThreadContext *tc) overrideGicv3CPUInterfacevirtual
SREGicv3CPUInterfaceprotected
StateGicv3CPUInterfaceprotected
TALL0Gicv3CPUInterfaceprotected
TALL1Gicv3CPUInterfaceprotected
TCGicv3CPUInterfaceprotected
TDIRGicv3CPUInterfaceprotected
TDSGicv3CPUInterfaceprotected
TSEIGicv3CPUInterfaceprotected
UGicv3CPUInterfaceprotected
UIEGicv3CPUInterfaceprotected
unserialize(CheckpointIn &cp) overrideGicv3CPUInterfaceprotectedvirtual
unserializeGlobals(CheckpointIn &cp)Serializablestatic
unserializeSection(CheckpointIn &cp, const char *name)Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)Serializableinline
update()Gicv3CPUInterfaceprotected
updateDistributor()Gicv3CPUInterfaceprotected
VAckCtlGicv3CPUInterfaceprotected
VBPR0Gicv3CPUInterfaceprotected
VBPR1Gicv3CPUInterfaceprotected
VCBPRGicv3CPUInterfaceprotected
VENG0Gicv3CPUInterfaceprotected
VENG1Gicv3CPUInterfaceprotected
VEOIMGicv3CPUInterfaceprotected
VFIQEnGicv3CPUInterfaceprotected
VGrp0DGicv3CPUInterfaceprotected
VGrp0DIEGicv3CPUInterfaceprotected
VGrp0EGicv3CPUInterfaceprotected
VGrp0EIEGicv3CPUInterfaceprotected
VGrp1DGicv3CPUInterfaceprotected
VGrp1DIEGicv3CPUInterfaceprotected
VGrp1EGicv3CPUInterfaceprotected
VGrp1EIEGicv3CPUInterfaceprotected
vINTIDGicv3CPUInterfaceprotected
VIRTUAL_NUM_LIST_REGSGicv3CPUInterfaceprotectedstatic
VIRTUAL_PREEMPTION_BITSGicv3CPUInterfaceprotectedstatic
VIRTUAL_PRIORITY_BITSGicv3CPUInterfaceprotectedstatic
virtualActivateIRQ(uint32_t lrIdx)Gicv3CPUInterfaceprotected
virtualDeactivateIRQ(int lrIdx)Gicv3CPUInterfaceprotected
virtualDropPriority()Gicv3CPUInterfaceprotected
virtualFindActive(uint32_t intid) constGicv3CPUInterfaceprotected
virtualGroupPriorityMask(Gicv3::GroupId group) constGicv3CPUInterfaceprotected
virtualHighestActivePriority() constGicv3CPUInterfaceprotected
virtualIncrementEOICount()Gicv3CPUInterfaceprotected
virtualIsEOISplitMode() constGicv3CPUInterfaceprotected
virtualUpdate()Gicv3CPUInterfaceprotected
VPMRGicv3CPUInterfaceprotected
~BaseISADevice()ArmISA::BaseISADeviceinlinevirtual
~Serializable()Serializablevirtual
Generated on Wed Sep 30 2020 14:02:25 for gem5 by doxygen 1.8.17