gem5  v20.1.0.0
RiscvISA::Decoder Member List

This is the complete list of members for RiscvISA::Decoder, including all inherited members.

alignedRiscvISA::Decoderprivate
compressed(ExtMachInst inst)RiscvISA::Decoderinline
decode(ExtMachInst mach_inst, Addr addr)RiscvISA::Decoder
decode(RiscvISA::PCState &nextPC)RiscvISA::Decoder
decodeInst(ExtMachInst mach_inst)RiscvISA::Decoder
Decoder(ISA *isa=nullptr)RiscvISA::Decoderinline
emiRiscvISA::Decoderprotected
fetchRomMicroop(MicroPC micropc, StaticInstPtr curMacroop)InstDecodervirtual
instDoneRiscvISA::Decoderprotected
instMapRiscvISA::Decoderprivate
instReady()RiscvISA::Decoderinline
midRiscvISA::Decoderprivate
moreRiscvISA::Decoderprivate
moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)RiscvISA::Decoder
needMoreBytes()RiscvISA::Decoderinline
process()RiscvISA::Decoderinline
reset()RiscvISA::Decoder
takeOverFrom(Decoder *old)RiscvISA::Decoderinline

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