#include <vector_register_file.hh>

Inheritance diagram for VectorRegisterFile:

Public Types
using	VecRegContainer = TheGpuISA::VecRegContainerU32

Public Types inherited from SimObject
typedef SimObjectParams	Params

Public Member Functions
	VectorRegisterFile (const VectorRegisterFileParams *p)

	~VectorRegisterFile ()

virtual bool	operandsReady (Wavefront *w, GPUDynInstPtr ii) const override

virtual void	scheduleWriteOperands (Wavefront *w, GPUDynInstPtr ii) override

virtual void	scheduleWriteOperandsFromLoad (Wavefront *w, GPUDynInstPtr ii) override

virtual void	waveExecuteInst (Wavefront *w, GPUDynInstPtr ii) override

void	setParent (ComputeUnit *_computeUnit) override

VecRegContainer &	readWriteable (int regIdx)

const VecRegContainer &	read (int regIdx) const

void	write (int regIdx, const VecRegContainer &value)

void	printReg (Wavefront *wf, int regIdx) const

Public Member Functions inherited from RegisterFile
	RegisterFile (const RegisterFileParams *p)

virtual	~RegisterFile ()

int	numRegs () const

virtual void	regStats () override
	Callback to set stat parameters. More...

virtual bool	regBusy (int idx) const

virtual void	markReg (int regIdx, bool value)

virtual void	enqRegFreeEvent (uint32_t regIdx, uint64_t delay)

virtual void	enqRegBusyEvent (uint32_t regIdx, uint64_t delay)

virtual bool	canScheduleReadOperands (Wavefront *w, GPUDynInstPtr ii)

virtual bool	canScheduleWriteOperands (Wavefront *w, GPUDynInstPtr ii)

virtual void	scheduleReadOperands (Wavefront *w, GPUDynInstPtr ii)

virtual bool	operandReadComplete (Wavefront *w, GPUDynInstPtr ii)

virtual bool	canScheduleWriteOperandsFromLoad (Wavefront *w, GPUDynInstPtr ii)

virtual void	exec ()

virtual std::string	dump () const

virtual void	dispatchInstruction (GPUDynInstPtr ii)

Public Member Functions inherited from SimObject
const Params *	params () const

	SimObject (const Params *_params)

virtual	~SimObject ()

virtual const std::string	name () const

virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

virtual Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a port with a given name and index. More...

virtual void	startup ()
	startup() is the final initialization call before simulation. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from Stats::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	resetStats ()
	Callback to reset stats. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (Stats::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Private Attributes
std::vector< VecRegContainer >	regFile

Additional Inherited Members
Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	serializeAll (const std::string &cpt_dir)
	Serializes all the SimObjects. More...

static void	unserializeGlobals (CheckpointIn &cp)

Protected Member Functions inherited from Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Attributes inherited from RegisterFile
ComputeUnit *	computeUnit

int	simdId

std::vector< bool >	busy

int	_numRegs

Stats::Scalar	registerReads

Stats::Scalar	registerWrites

Stats::Scalar	sramReads

Stats::Scalar	sramWrites

Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Detailed Description

Definition at line 46 of file vector_register_file.hh.

Member Typedef Documentation

◆ VecRegContainer

using VectorRegisterFile::VecRegContainer = TheGpuISA::VecRegContainerU32

Definition at line 49 of file vector_register_file.hh.

Constructor & Destructor Documentation

◆ VectorRegisterFile()

VectorRegisterFile::VectorRegisterFile ( const VectorRegisterFileParams * p )

Definition at line 47 of file vector_register_file.cc.

References RegisterFile::numRegs(), X86ISA::reg, and regFile.

◆ ~VectorRegisterFile()

VectorRegisterFile::~VectorRegisterFile ( )

inline

Definition at line 52 of file vector_register_file.hh.

Member Function Documentation

◆ operandsReady()

bool VectorRegisterFile::operandsReady	(	Wavefront *	w,
		GPUDynInstPtr	ii
	)		const

overridevirtual

Reimplemented from RegisterFile.

Definition at line 58 of file vector_register_file.cc.

References RegisterFile::computeUnit, DPRINTF, ArmISA::i, ArmISA::j, RegisterManager::mapVgpr(), RegisterFile::regBusy(), ComputeUnit::registerManager, and MipsISA::w.

◆ printReg()

void VectorRegisterFile::printReg	(	Wavefront *	wf,
		int	regIdx
	)		const

inline

Definition at line 89 of file vector_register_file.hh.

References DPRINTF, Wavefront::execMask(), ArmISA::NumVecElemPerVecReg, regFile, Wavefront::simdId, Wavefront::wfDynId, and Wavefront::wfSlotId.

◆ read()

const VecRegContainer& VectorRegisterFile::read ( int regIdx ) const

inline

Definition at line 76 of file vector_register_file.hh.

References regFile.

◆ readWriteable()

VecRegContainer& VectorRegisterFile::readWriteable ( int regIdx )

inline

Definition at line 69 of file vector_register_file.hh.

References regFile.

◆ scheduleWriteOperands()

void VectorRegisterFile::scheduleWriteOperands	(	Wavefront *	w,
		GPUDynInstPtr	ii
	)

overridevirtual

if the instruction is a load with EXEC = 0, then we do not mark the reg. we do this to avoid a deadlock that can occur because a load reserves its destination regs before checking its exec mask, and in the case it is 0, it will not send/recv any packets, and therefore it will never free its dest reg(s).

Reimplemented from RegisterFile.

Definition at line 87 of file vector_register_file.cc.

References RegisterFile::computeUnit, ArmISA::i, ArmISA::j, RegisterManager::mapVgpr(), RegisterFile::markReg(), ComputeUnit::registerManager, and MipsISA::w.

◆ scheduleWriteOperandsFromLoad()

void VectorRegisterFile::scheduleWriteOperandsFromLoad	(	Wavefront *	w,
		GPUDynInstPtr	ii
	)

overridevirtual

Reimplemented from RegisterFile.

Definition at line 180 of file vector_register_file.cc.

References Clocked::clockPeriod(), RegisterFile::computeUnit, RegisterFile::enqRegFreeEvent(), ArmISA::i, ArmISA::j, RegisterManager::mapVgpr(), ArmISA::mask, ComputeUnit::registerManager, RegisterFile::registerWrites, RegisterFile::sramWrites, and MipsISA::w.

◆ setParent()

void VectorRegisterFile::setParent ( ComputeUnit * _computeUnit )

inlineoverridevirtual

Reimplemented from RegisterFile.

Definition at line 62 of file vector_register_file.hh.

References RegisterFile::setParent().

◆ waveExecuteInst()

void VectorRegisterFile::waveExecuteInst	(	Wavefront *	w,
		GPUDynInstPtr	ii
	)

overridevirtual

Reimplemented from RegisterFile.

Definition at line 124 of file vector_register_file.cc.

References RegisterFile::computeUnit, Clocked::cyclesToTicks(), ComputeUnit::dpBypassLength(), RegisterFile::enqRegFreeEvent(), ArmISA::i, ArmISA::j, RegisterManager::mapVgpr(), ArmISA::mask, ComputeUnit::registerManager, RegisterFile::registerReads, RegisterFile::registerWrites, RegisterFile::sramReads, RegisterFile::sramWrites, and MipsISA::w.

◆ write()

void VectorRegisterFile::write	(	int	regIdx,
		const VecRegContainer &	value
	)

inline

Definition at line 83 of file vector_register_file.hh.

References regFile.

Member Data Documentation

◆ regFile

std::vector<VecRegContainer> VectorRegisterFile::regFile

private

Definition at line 106 of file vector_register_file.hh.

Referenced by printReg(), read(), readWriteable(), VectorRegisterFile(), and write().

The documentation for this class was generated from the following files:

gpu-compute/vector_register_file.hh
gpu-compute/vector_register_file.cc

Public Types

Public Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ VecRegContainer

Constructor & Destructor Documentation

◆ VectorRegisterFile()

◆ ~VectorRegisterFile()

Member Function Documentation

◆ operandsReady()

◆ printReg()

◆ read()

◆ readWriteable()

◆ scheduleWriteOperands()

◆ scheduleWriteOperandsFromLoad()

◆ setParent()

◆ waveExecuteInst()

◆ write()

Member Data Documentation

◆ regFile