gem5  v20.1.0.0
datatypes.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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20 /*****************************************************************************
21 
22  datatypes.h --
23 
24  Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 
39 #include "common.h"
40 
41 SC_MODULE( datatypes )
42 {
43  SC_HAS_PROCESS( datatypes );
44 
45  sc_in_clk clk;
46 
47  const sc_signal<bool>& reset ;
48  const sc_signal_bool_vector& in_value1;
49  const sc_signal_bool_vector& in_value2;
50  const sc_signal_bool_vector& in_value3;
51  const sc_signal_bool_vector& in_value4;
52  const sc_signal<bool>& in_valid;
53  sc_signal_bool_vector& out_value1;
54  sc_signal_bool_vector& out_value2;
55  sc_signal_bool_vector& out_value3;
56  sc_signal_bool_vector& out_value4;
57  sc_signal<bool>& out_valid;
58 
59  //
60  // Constructor
61  //
62 
63  datatypes(
64  sc_module_name NAME, // referense name
65  sc_clock& CLK, // clock
66  const sc_signal<bool>& RESET,
67  const sc_signal_bool_vector& IN_VALUE1,
68  const sc_signal_bool_vector& IN_VALUE2,
69  const sc_signal_bool_vector& IN_VALUE3,
70  const sc_signal_bool_vector& IN_VALUE4,
71  const sc_signal<bool>& IN_VALID, // Input port
72  sc_signal_bool_vector& OUT_VALUE1,
73  sc_signal_bool_vector& OUT_VALUE2,
74  sc_signal_bool_vector& OUT_VALUE3,
75  sc_signal_bool_vector& OUT_VALUE4,
76  sc_signal<bool>& OUT_VALID // Input port
77  )
78  :
79  reset (RESET),
80  in_value1 (IN_VALUE1),
81  in_value2 (IN_VALUE2),
82  in_value3 (IN_VALUE3),
83  in_value4 (IN_VALUE4),
84  in_valid (IN_VALID),
85  out_value1 (OUT_VALUE1),
86  out_value2 (OUT_VALUE2),
87  out_value3 (OUT_VALUE3),
88  out_value4 (OUT_VALUE4),
89  out_valid (OUT_VALID)
90  {
91  clk (CLK);
92  SC_CTHREAD( entry, clk.pos() );
93  reset_signal_is(reset,true);
94  };
95 
96  //
97 
98  void entry ();
99 
100 };
101 
102 // EOF
sc_signal_bool_vector
sc_signal< sc_bv< 8 > > sc_signal_bool_vector
Definition: common.h:43
Stats::reset
void reset()
Definition: statistics.cc:569
SC_MODULE
SC_MODULE(datatypes)
Definition: datatypes.h:40
common.h
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319
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