gem5  v20.1.0.0
integer.cc
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28 
30 
31 using namespace std;
32 using namespace PowerISA;
33 
34 string
35 IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
36 {
37  stringstream ss;
38  bool printDest = true;
39  bool printSrcs = true;
40  bool printSecondSrc = true;
41 
42  // Generate the correct mnemonic
43  string myMnemonic(mnemonic);
44 
45  // Special cases
46  if (!myMnemonic.compare("or") && _srcRegIdx[0] == _srcRegIdx[1]) {
47  myMnemonic = "mr";
48  printSecondSrc = false;
49  } else if (!myMnemonic.compare("mtlr") || !myMnemonic.compare("cmpi")) {
50  printDest = false;
51  } else if (!myMnemonic.compare("mflr")) {
52  printSrcs = false;
53  }
54 
55  // Additional characters depending on isa bits being set
56  if (oeSet) myMnemonic = myMnemonic + "o";
57  if (rcSet) myMnemonic = myMnemonic + ".";
58  ccprintf(ss, "%-10s ", myMnemonic);
59 
60  // Print the first destination only
61  if (_numDestRegs > 0 && printDest) {
62  printReg(ss, _destRegIdx[0]);
63  }
64 
65  // Print the (possibly) two source registers
66  if (_numSrcRegs > 0 && printSrcs) {
67  if (_numDestRegs > 0 && printDest) {
68  ss << ", ";
69  }
70  printReg(ss, _srcRegIdx[0]);
71  if (_numSrcRegs > 1 && printSecondSrc) {
72  ss << ", ";
73  printReg(ss, _srcRegIdx[1]);
74  }
75  }
76 
77  return ss.str();
78 }
79 
80 
81 string
82 IntImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
83 {
84  stringstream ss;
85 
86  // Generate the correct mnemonic
87  string myMnemonic(mnemonic);
88 
89  // Special cases
90  if (!myMnemonic.compare("addi") && _numSrcRegs == 0) {
91  myMnemonic = "li";
92  } else if (!myMnemonic.compare("addis") && _numSrcRegs == 0) {
93  myMnemonic = "lis";
94  }
95  ccprintf(ss, "%-10s ", myMnemonic);
96 
97  // Print the first destination only
98  if (_numDestRegs > 0) {
99  printReg(ss, _destRegIdx[0]);
100  }
101 
102  // Print the source register
103  if (_numSrcRegs > 0) {
104  if (_numDestRegs > 0) {
105  ss << ", ";
106  }
107  printReg(ss, _srcRegIdx[0]);
108  }
109 
110  // Print the immediate value last
111  ss << ", " << (int32_t)imm;
112 
113  return ss.str();
114 }
115 
116 
117 string
118 IntShiftOp::generateDisassembly(
119  Addr pc, const Loader::SymbolTable *symtab) const
120 {
121  stringstream ss;
122 
123  ccprintf(ss, "%-10s ", mnemonic);
124 
125  // Print the first destination only
126  if (_numDestRegs > 0) {
127  printReg(ss, _destRegIdx[0]);
128  }
129 
130  // Print the first source register
131  if (_numSrcRegs > 0) {
132  if (_numDestRegs > 0) {
133  ss << ", ";
134  }
135  printReg(ss, _srcRegIdx[0]);
136  }
137 
138  // Print the shift
139  ss << ", " << sh;
140 
141  return ss.str();
142 }
143 
144 
145 string
146 IntRotateOp::generateDisassembly(
147  Addr pc, const Loader::SymbolTable *symtab) const
148 {
149  stringstream ss;
150 
151  ccprintf(ss, "%-10s ", mnemonic);
152 
153  // Print the first destination only
154  if (_numDestRegs > 0) {
155  printReg(ss, _destRegIdx[0]);
156  }
157 
158  // Print the first source register
159  if (_numSrcRegs > 0) {
160  if (_numDestRegs > 0) {
161  ss << ", ";
162  }
163  printReg(ss, _srcRegIdx[0]);
164  }
165 
166  // Print the shift, mask begin and mask end
167  ss << ", " << sh << ", " << mb << ", " << me;
168 
169  return ss.str();
170 }
ArmISA::sh
Bitfield< 8, 7 > sh
Definition: miscregs_types.hh:654
Loader::SymbolTable
Definition: symtab.hh:59
integer.hh
ArmISA::ss
Bitfield< 21 > ss
Definition: miscregs_types.hh:56
PowerISA
Definition: decoder.cc:31
PowerISA::mb
Bitfield< 10, 6 > mb
Definition: types.hh:49
ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:141
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
PowerISA::me
Bitfield< 5, 1 > me
Definition: types.hh:50
std
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:127

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