gem5  v20.1.0.0
scalar_memory_pipeline.cc
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35 
37 
38 #include "debug/GPUMem.hh"
39 #include "debug/GPUReg.hh"
43 #include "gpu-compute/shader.hh"
44 #include "gpu-compute/wavefront.hh"
45 
46 ScalarMemPipeline::ScalarMemPipeline(const ComputeUnitParams* p,
47  ComputeUnit &cu)
48  : computeUnit(cu), _name(cu.name() + ".ScalarMemPipeline"),
49  queueSize(p->scalar_mem_queue_size),
50  inflightStores(0), inflightLoads(0)
51 {
52 }
53 
54 void
56 {
57  // afind oldest scalar request whose data has arrived
58  GPUDynInstPtr m = !returnedLoads.empty() ? returnedLoads.front() :
59  !returnedStores.empty() ? returnedStores.front() : nullptr;
60 
61  Wavefront *w = nullptr;
62 
63  bool accessSrf = true;
64  // check the SRF to see if the operands of a load (or load component
65  // of an atomic) are accessible
66  if ((m) && (m->isLoad() || m->isAtomicRet())) {
67  w = m->wavefront();
68 
69  accessSrf =
70  w->computeUnit->srf[w->simdId]->
71  canScheduleWriteOperandsFromLoad(w, m);
72  }
73 
74  if ((!returnedStores.empty() || !returnedLoads.empty()) &&
75  m->latency.rdy() && computeUnit.scalarMemToSrfBus.rdy() &&
76  accessSrf &&
79 
80  w = m->wavefront();
81 
82  if (m->isLoad() || m->isAtomicRet()) {
83  w->computeUnit->srf[w->simdId]->
84  scheduleWriteOperandsFromLoad(w, m);
85  }
86 
87  m->completeAcc(m);
88  w->decLGKMInstsIssued();
89 
90  if (m->isLoad() || m->isAtomic()) {
91  returnedLoads.pop();
92  assert(inflightLoads > 0);
93  --inflightLoads;
94  } else {
95  returnedStores.pop();
96  assert(inflightStores > 0);
98  }
99 
100  // Decrement outstanding register count
101  computeUnit.shader->ScheduleAdd(&w->outstandingReqs, m->time, -1);
102 
103  if (m->isStore() || m->isAtomic()) {
104  computeUnit.shader->ScheduleAdd(&w->scalarOutstandingReqsWrGm,
105  m->time, -1);
106  }
107 
108  if (m->isLoad() || m->isAtomic()) {
109  computeUnit.shader->ScheduleAdd(&w->scalarOutstandingReqsRdGm,
110  m->time, -1);
111  }
112 
113  // Mark write bus busy for appropriate amount of time
116  w->computeUnit->scalarMemUnit.set(m->time);
117  }
118 
119  // If pipeline has executed a global memory instruction
120  // execute global memory packets and issue global
121  // memory packets to DTLB
122  if (!issuedRequests.empty()) {
123  GPUDynInstPtr mp = issuedRequests.front();
124  if (mp->isLoad() || mp->isAtomic()) {
125 
126  if (inflightLoads >= queueSize) {
127  return;
128  } else {
129  ++inflightLoads;
130  }
131  } else {
132  if (inflightStores >= queueSize) {
133  return;
134  } else {
135  ++inflightStores;
136  }
137  }
138  mp->initiateAcc(mp);
139  issuedRequests.pop();
140 
141  DPRINTF(GPUMem, "CU%d: WF[%d][%d] Popping scalar mem_op\n",
142  computeUnit.cu_id, mp->simdId, mp->wfSlotId);
143  }
144 }
145 
146 void
148 {
149 }
shader.hh
ScalarMemPipeline::computeUnit
ComputeUnit & computeUnit
Definition: scalar_memory_pipeline.hh:91
ScalarMemPipeline::returnedLoads
std::queue< GPUDynInstPtr > returnedLoads
Definition: scalar_memory_pipeline.hh:110
compute_unit.hh
ScalarMemPipeline::returnedStores
std::queue< GPUDynInstPtr > returnedStores
Definition: scalar_memory_pipeline.hh:106
ComputeUnit::cu_id
int cu_id
Definition: compute_unit.hh:289
ScalarMemPipeline::issuedRequests
std::queue< GPUDynInstPtr > issuedRequests
Definition: scalar_memory_pipeline.hh:102
Shader::coissue_return
int coissue_return
Definition: shader.hh:222
wavefront.hh
WaitClass::rdy
bool rdy(Cycles cycles=Cycles(0)) const
Definition: misc.hh:90
ComputeUnit
Definition: compute_unit.hh:198
MipsISA::w
Bitfield< 0 > w
Definition: pra_constants.hh:278
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
ScalarMemPipeline::inflightStores
int inflightStores
Definition: scalar_memory_pipeline.hh:97
WaitClass::set
void set(uint64_t i)
Definition: misc.hh:79
scalar_register_file.hh
gpu_dyn_inst.hh
ComputeUnit::scalarMemUnit
WaitClass scalarMemUnit
Definition: compute_unit.hh:238
ScalarMemPipeline::exec
void exec()
Definition: scalar_memory_pipeline.cc:55
scalar_memory_pipeline.hh
ScalarMemPipeline::ScalarMemPipeline
ScalarMemPipeline(const ComputeUnitParams *p, ComputeUnit &cu)
Definition: scalar_memory_pipeline.cc:46
name
const std::string & name()
Definition: trace.cc:50
ScalarMemPipeline::queueSize
int queueSize
Definition: scalar_memory_pipeline.hh:93
ComputeUnit::scalarMemToSrfBus
WaitClass scalarMemToSrfBus
Definition: compute_unit.hh:234
Shader::ScheduleAdd
void ScheduleAdd(int *val, Tick when, int x)
Definition: shader.cc:431
Wavefront
Definition: wavefront.hh:57
ScalarMemPipeline::inflightLoads
int inflightLoads
Definition: scalar_memory_pipeline.hh:98
ScalarMemPipeline::regStats
void regStats()
Definition: scalar_memory_pipeline.cc:147
GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition: misc.hh:48
ArmISA::mp
Bitfield< 11 > mp
Definition: miscregs_types.hh:762
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
ComputeUnit::shader
Shader * shader
Definition: compute_unit.hh:356
ArmISA::m
Bitfield< 0 > m
Definition: miscregs_types.hh:389

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