gem5
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systemc
tests
systemc
misc
unit
data
datawidth_unsigned
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stimgen.h
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Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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more contributor license agreements. See the NOTICE file distributed
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with this work for additional information regarding copyright ownership.
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Accellera licenses this file to you under the Apache License, Version 2.0
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(the "License"); you may not use this file except in compliance with the
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License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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implied. See the License for the specific language governing
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permissions and limitations under the License.
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/*****************************************************************************
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stimgen.h --
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Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
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*****************************************************************************/
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/*****************************************************************************
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MODIFICATION LOG - modifiers, enter your name, affiliation, date and
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changes you are making here.
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Name, Affiliation, Date:
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Description of Modification:
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*****************************************************************************/
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/************************************/
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/* Interface Filename: stimgen.h */
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/************************************/
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#include "
common.h
"
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SC_MODULE
( stimgen )
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{
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SC_HAS_PROCESS
( stimgen );
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sc_in_clk
clk;
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// Inputs
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const
signal_bool_vector4
& result;
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// Outputs
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signal_bool_vector6
& in1;
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signal_bool_vector6
& in2;
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sc_signal<bool>& ready;
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// Constructor
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stimgen (sc_module_name NAME,
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sc_clock& TICK,
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const
signal_bool_vector4
& RESULT,
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signal_bool_vector6
& IN1,
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signal_bool_vector6
& IN2,
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sc_signal<bool>& READY )
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:
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result (RESULT),
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in1 (IN1),
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in2 (IN2),
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ready (READY)
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{
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clk (TICK);
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SC_CTHREAD
( entry, clk.pos() );
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}
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void
entry();
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};
signal_bool_vector6
sc_signal< bool_vector6 > signal_bool_vector6
Definition:
common.h:46
signal_bool_vector4
sc_signal< bool_vector4 > signal_bool_vector4
Definition:
common.h:46
SC_MODULE
SC_MODULE(stimgen)
Definition:
stimgen.h:44
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition:
sc_clock.hh:116
common.h
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition:
sc_module.hh:297
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition:
sc_module.hh:319
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