gem5  v20.1.0.0
datawidth.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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20 /*****************************************************************************
21 
22  datawidth.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
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33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38  /**************************************/
39  /* Interface Filename: datawidth.h */
40  /**************************************/
41 
42 #include "common.h"
43 
44 SC_MODULE( datawidth )
45 {
46  SC_HAS_PROCESS( datawidth );
47 
48  sc_in_clk clk;
49 
50  // Inputs
51  const sc_signal_bool_vector6& in1;
52  const sc_signal_bool_vector6& in2;
53  const sc_signal<bool>& ready;
54  // Outputs
55  sc_signal_bool_vector7& result;
56 
57  // Constructor
58  datawidth (sc_module_name NAME,
59  sc_clock& TICK,
60  const sc_signal_bool_vector6& IN1,
61  const sc_signal_bool_vector6& IN2,
62  const sc_signal<bool>& READY,
63  sc_signal_bool_vector7& RESULT )
64 
65  :
66  in1 (IN1),
67  in2 (IN2),
68  ready (READY),
69  result (RESULT)
70 
71  {
72  clk (TICK);
73  SC_CTHREAD( entry, clk.pos() );
74  }
75 
76  void entry();
77 };
sc_signal_bool_vector7
sc_signal< sc_bv< 7 > > sc_signal_bool_vector7
Definition: common.h:46
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
sc_signal_bool_vector6
sc_signal< sc_bv< 6 > > sc_signal_bool_vector6
Definition: common.h:44
common.h
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:297
SC_MODULE
SC_MODULE(datawidth)
Definition: datawidth.h:44
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:319

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