- c -

c : ArmISA::PMU , AtomicGeneric3Op< T > , AtomicGenericPair3Op< T > , AtomicOpCAS< T > , Coeff8 , Coeff8x8 , Compressed , Cycles , MathExpr::OpSearch
C0 : MipsISA::PTE , PowerISA::PTE
c0_config : SparcISA::TLB
c0_tsb_ps0 : SparcISA::TLB
c0_tsb_ps1 : SparcISA::TLB
C1 : MipsISA::PTE , PowerISA::PTE
cache : AddrRangeMap< V, max_cache_size > , BaseCache::CacheCmdStats , BaseCache::CacheReqPacketQueue , BaseCache::CacheStats , BaseCache::CpuSidePort , BaseCache::MemSidePort , Prefetcher::Base
cacheAsi : SparcISA::TLB
cacheBlkSize : DefaultFetch< Impl >
cacheBlocked : DefaultFetch< Impl >
cacheBlockMask : AtomicSimpleCPU::AtomicCPUDPort , LSQUnit< Impl > , Minor::LSQ , TimingSimpleCPU::DcachePort
cacheBlockRoundTrip : Shader
CacheChunkBytes : DecodeCache::AddrMap< Value, CacheChunkShift >
cachedDisassembly : StaticInst
cachedLocations : SnoopFilter
cachedMsrIntersection : X86KvmCPU
cachedPC : PowerISA::PCDependentDisassembly
cachedSymtab : PowerISA::PCDependentDisassembly
cacheEntry : SparcISA::TLB
cacheLineBits : ComputeUnit , FetchUnit::FetchBufDesc
cacheLines : DefaultFetch< Impl >::FetchStatGroup , MemFootprintProbe
cacheLinesAll : MemFootprintProbe
cacheLineSize : FetchUnit::FetchBufDesc , HybridGen , PCIConfig , StochasticGen
cacheLineSizeLg2 : MemFootprintProbe
cacheLoadPorts : LSQ< Impl >
cacheMiss : Prefetcher::Base::PrefetchInfo
cachePnt : IGbE::DescCache< T >
cachePort : GarnetSyntheticTraffic
cacheSnoop : Prefetcher::Queued
cacheState : SparcISA::TLB
cacheStore : SimpleCache
cacheStorePorts : LSQ< Impl >
cacheSwizzle : Gcn3ISA::BufferRsrcDescriptor
cacheTracking : FALRU
cacheValid : SparcISA::TLB
cachingPage : UFSHostDevice::UFSSCSIDevice
calc : StackDistProbe
call32 : ArmSemihosting::SemiCall
call64 : ArmSemihosting::SemiCall
call_convention : AMDKernelCode
callback : EventFunctionWrapper
caller : m5::Coroutine< Arg, Ret >
callerFiber : m5::Coroutine< Arg, Ret >::CallerType
calls : ArmSemihosting
canEarlyIssue : Minor::MinorDynInst
canHandleInterrupts : DefaultCommit< Impl >
canMergeWrites : MSHR::TargetList
cantForwardFromFUIndices : Minor::FUPipeline , MinorFU
capabilityList : FuncUnit , FUPool , Minor::FUPipeline , MinorOpClassSet
capabilityPtr : PCIConfig
capacitors : ThermalModel
capacity : Minor::Queue< ElemType, ReportTraits, BubbleTraits > , SimpleCache , VirtIOBlock::Config
capacityLower : UFSHostDevice::UFSSCSIDevice
capacityUpper : UFSHostDevice::UFSSCSIDevice
caplen : pcap_pkthdr
captureCurrentFrame : VncInput
captureEnabled : VncInput
captureImage : VncInput
captureLastHash : VncInput
captureOutputDirectory : VncInput
cardbusCIS : PCIConfig
cascadeBits : X86ISA::I8259
cascadeMode : X86ISA::I8259
cause : CountedExitEvent , GenericHtmFailureFault , GlobalSimLoopExitEvent , LocalSimLoopExitEvent , MipsISA::RemoteGDB::MipsGdbRegCache
CBPR : Gicv3CPUInterface
CBPR_EL1NS : Gicv3CPUInterface
CBPR_EL1S : Gicv3CPUInterface
cchip : Malta
ccList : UnifiedFreeList
ccMap : UnifiedRenameMap
ccRegFile : PhysRegFile
ccRegfileReads : FullO3CPU< Impl >
ccRegfileWrites : FullO3CPU< Impl >
ccRegIds : Iris::ThreadContext , PhysRegFile
ccRegIdxNameMap : FastModel::CortexA76TC
ccRegs : SimpleThread
ccsr : dp_regs
cct : Gicv3Its
cdbg_user : AMDKernelCode
cdcLatency : NetworkBridge
cdf : Stats::ScalarPrint
cdFetches : SMMUv3
cdfstrSpaces : Stats::ScalarPrint
cdL1Fetches : SMMUv3
ce : CopyEngine::CopyEngineChannel
cePort : CopyEngine::CopyEngineChannel
ch_b : PixelConverter
ch_g : PixelConverter
ch_r : PixelConverter
chain : ArmISA::ISA::MiscRegLUTEntryInitializer
chan : CopyEngine
chanCount : CopyEngineReg::Regs
changed : Trace::ArmNativeTrace::ThreadState
changedPC : CheckerCPU
changedROBNumEntries : DefaultCommit< Impl >
channelId : CopyEngine::CopyEngineChannel
char_to_logic : sc_dt::sc_logic
characteristicExtBytes : X86ISA::SMBios::BiosInformation
characteristics : X86ISA::SMBios::BiosInformation
checkEmptyROB : DefaultCommit< Impl >
checker : BaseSimpleCPU , FullO3CPU< Impl >
checkerCPU : CheckerThreadContext< TC >
checkerTC : CheckerThreadContext< TC >
checkLoads : LSQUnit< Impl >
checkR11 : Trace::X86NativeTrace
checkRcx : Trace::X86NativeTrace
checkStartEvent : RubyTester
child : CowDiskImage , SimpleInitiatorWrapper , SimpleTargetWrapper
childClearTID : Process
children : ClockDomain , ProfileNode , sc_gem5::Object
choiceCounters : BiModeBP
choiceCtrBits : BiModeBP , TournamentBP
choiceCtrs : TournamentBP
choiceHistoryMask : BiModeBP , TournamentBP
choicePredictorSize : BiModeBP , TournamentBP
choiceThreshold : BiModeBP , TournamentBP
chooserConfWidth : StatisticalCorrector
chunk : LdsChunk
chunkIdx : X86ISA::Decoder
chunkMap : DecodeCache::AddrMap< Value, CacheChunkShift > , LdsState
chunks : Compressor::Perfect::CompData , X86ISA::Decoder::InstBytes
chunkSize : ChunkGenerator , Prefetcher::IrregularStreamBuffer
chunkSizeBits : Compressor::Base
ci : TAGEBase::BranchInfo
cidBits : Gicv3Its
cil : Gicv3Its
ckptRestore : DistIface::RecvScheduler
CLAMP : Gcn3ISA::InFmt_VOP3 , Gcn3ISA::InFmt_VOP3_SDST_ENC , Gcn3ISA::InFmt_VOP_SDWA
classCode : PCIConfig
ClcdCrsrClip : Pl111
clcdCrsrClip : Pl111
ClcdCrsrConfig : Pl111
clcdCrsrConfig : Pl111
ClcdCrsrCtrl : Pl111
clcdCrsrCtrl : Pl111
ClcdCrsrIcr : Pl111
clcdCrsrIcr : Pl111
ClcdCrsrImsc : Pl111
clcdCrsrImsc : Pl111
ClcdCrsrMis : Pl111
clcdCrsrMis : Pl111
ClcdCrsrPalette0 : Pl111
clcdCrsrPalette0 : Pl111
ClcdCrsrPalette1 : Pl111
clcdCrsrPalette1 : Pl111
ClcdCrsrRis : Pl111
clcdCrsrRis : Pl111
ClcdCrsrXY : Pl111
clcdCrsrXY : Pl111
cleanupEvent : TLBCoalescer , X86ISA::GpuTLB
cleanupQueue : TLBCoalescer , X86ISA::GpuTLB
clearFetchFault : DefaultFetchDefaultDecode< Impl >
clearInterrupt : TimeBufStruct< Impl >::commitComm
clearPeriod : StoreSet
clearReq : MultiSocketSimpleSwitchAT::ConnectionInfo
client : Iris::ThreadContext
clk : fun , memory , test
clk_in : Pl050
clkdiv : Pl050
clkn : testbench
clkn2 : testbench
clkp : testbench
clkp2 : testbench
clkResyncDelay : DRAMInterface
clksel : Pl111
clock : ClockDomain::ClockDomainStats , Sp804::Timer
clock_data : MC146818
clock_remainder : ArmISA::PMU
clockChanged : FastModel::ScxEvsCortexA76< Types >
clockDivider : DerivedClockDomain
clockDomain : Clocked , X86ISA::Interrupts
clocked_object : PowerModel , PowerModelState
clockedObject : WaitClass
clockEvent : Iris::BaseCPU
clockID : PosixKvmTimer
clockPeriod : FastModel::ScxEvsCortexA76< Types >
clockRateControl : FastModel::ScxEvsCortexA76< Types >
ClrImportant : BmpWriter::InfoHeaderV1
ClrUsed : BmpWriter::InfoHeaderV1
cltn : sc_core::sc_attr_cltn , sc_gem5::Object
clusivity : BaseCache
cluster : FastModel::CortexA76
cm : ArmISA::DataAbort , ArmISA::Watchpoint
cmap : Stats::SparseHistData , Stats::SparseHistStor
cmd : BaseCache::CacheStats , BaseRemoteGDB::GdbCommand::Context , MemCmd , Packet , ProbePoints::PacketInfo , SMMUCommandExecProcess , TraceCPU::FixedRetryGen::TraceElement , TraceGen::TraceElement
cmd_byte : BaseRemoteGDB::GdbCommand::Context
cmdBytes : IdeDisk
cmdBytesLeft : IdeDisk
cmdDispatcher : ItsCommand
cmdLine : ArmSemihosting
cmdList : DRAMInterface::Rank
cmdq_base : SMMURegs
cmdq_cons : SMMURegs
cmdq_prod : SMMURegs
cmdReg : IdeDisk
cmdsts : ns_desc32 , ns_desc64
CMDUCMDARG1 : UFSHostDevice::HCIMem
CMDUCMDARG2 : UFSHostDevice::HCIMem
CMDUCMDARG3 : UFSHostDevice::HCIMem
CMDUICCMDR : UFSHostDevice::HCIMem
cmos : SouthBridge
cmpEnable : A9GlobalTimer::Timer
cmpVal : A9GlobalTimer::Timer
cmpValEvent : A9GlobalTimer::Timer
cntfrq : GenericTimer::CoreTimers
cnthctl : GenericTimer::CoreTimers
cnthpirq : FastModel::ScxEvsCortexA76< Types >
cnthvirq : FastModel::ScxEvsCortexA76< Types >
cntkctl : GenericTimer::CoreTimers
cntpnsirq : FastModel::ScxEvsCortexA76< Types >
cntpsirq : FastModel::ScxEvsCortexA76< Types >
cnttidr : GenericTimerMem
cntvirq : FastModel::ScxEvsCortexA76< Types >
coalescedAccesses : TLBCoalescer
coalescedRxDesc : EtherDevice
coalescedRxIdle : EtherDevice
coalescedRxOk : EtherDevice
coalescedRxOrn : EtherDevice
coalescedSwi : EtherDevice
coalescedTable : GPUCoalescer
coalescedTotal : EtherDevice
coalescedTxDesc : EtherDevice
coalescedTxIdle : EtherDevice
coalescedTxOk : EtherDevice
coalesceLimit : WriteAllocator
coalescer : TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , UncoalescedTable
coalescerFIFO : TLBCoalescer
coalescerToVrfBusWidth : ComputeUnit
coalescingWindow : GPUCoalescer , TLBCoalescer
coalsrLineAddresses : Shader
coBridge : NetworkBridge
code : Compressor::DictionaryCompressor< T >::Pattern , EmbeddedPython , GlobalSimLoopExitEvent , HUFFMTBL_ENTRY , LocalSimLoopExitEvent , MipsISA::MipsFaultBase::FaultVals
codeAddress : HSAQueueEntry
coeff : MultiperspectivePerceptron::HistorySpec
coissue_return : Shader
cols : VirtIOConsole::Config
comInstEventQueue : Iris::ThreadContext , O3ThreadState< Impl > , SimpleThread
command : CommandReg , CopyEngineReg::ChanRegs , CopyEngineReg::DmaDesc , dp_regs , HDLcd , PCIConfig
Command : Sinic::Device
command_map : BaseRemoteGDB
commandByte : X86ISA::I8042
commandDescBaseAddrHi : UFSHostDevice::UTPTransferReqDesc
commandDescBaseAddrLo : UFSHostDevice::UTPTransferReqDesc
commandEvent : Gicv3Its
commandExecutor : SMMUv3
commandInfo : MemCmd
commandLast : X86ISA::I8042
commandLine : KernelWorkload
commandPort : X86ISA::I8042
commandUPIU : UFSHostDevice::UTPTransferCMDDesc
commandWindow : MemCtrl
commirq : FastModel::ScxEvsCortexA76< Types >
commit : DefaultRename< Impl >::Stalls , ElasticTrace::TraceInfo , FullO3CPU< Impl >
commit_ptr : DefaultRename< Impl >
commitEligibleSamples : DefaultCommit< Impl >::CommitStats
commitInfo : TimeBufStruct< Impl >
commitLimit : Minor::Execute
commitNonSpecStalls : DefaultCommit< Impl >::CommitStats
commitPolicy : DefaultCommit< Impl >
commitPriority : Minor::Execute
commitRenameMap : FullO3CPU< Impl >
commitSquashedInsts : DefaultCommit< Impl >::CommitStats
commitStatus : DefaultCommit< Impl >
committedInsts : BaseKvmCPU::StatGroup , FullO3CPU< Impl >
committedInstType : DefaultCommit< Impl >::CommitStats , Minor::MinorStats
committedMaps : DefaultRename< Impl >::RenameStats
committedOps : FullO3CPU< Impl >
committedStores : DefaultCommit< Impl >
commitTick : ElasticTrace::TraceInfo
commitToDecodeDelay : DefaultDecode< Impl >
commitToFetchDelay : DefaultFetch< Impl >
commitToIEWDelay : DefaultCommit< Impl > , DefaultIEW< Impl > , InstructionQueue< Impl >
commitToRenameDelay : DefaultRename< Impl >
commitWidth : DefaultCommit< Impl > , DefaultRename< Impl >
commPage : ArmFreebsdProcess32 , ArmLinuxProcess32
comp : TAGEBase::FoldedHistory
compData : Compressor::Multi::MultiCompData
compDelay : ElasticTrace::TraceInfo , TraceCPU::ElasticDataGen::GraphNode
compLength : TAGEBase::FoldedHistory
complete : ArmISA::Stage2LookUp , MemChecker::Transaction , MemChecker::WriteCluster
COMPLETED : ArmISA::TableWalker
completed : MemDepUnit< MemDepPred, Impl >::MemDepEntry
completedWfs : ComputeUnit
completedWGs : ComputeUnit
completeMax : MemChecker::WriteCluster
completion_signal : _hsa_agent_dispatch_packet_s , _hsa_barrier_and_packet_s , _hsa_barrier_or_packet_s , _hsa_dispatch_packet_s , hsa_agent_dispatch_packet_s , hsa_barrier_and_packet_s , hsa_barrier_or_packet_s , hsa_kernel_dispatch_packet_s
completionAddr : CopyEngineReg::ChanRegs
completionAddress : IGbE::TxDescCache
completionDataReg : CopyEngine::CopyEngineChannel
completionEnabled : IGbE::TxDescCache
completionEvent : DmaPort::DmaReqState
COMPR : Gcn3ISA::InFmt_EXP
compressedSize : Compressor::Perfect
Compression : BmpWriter::InfoHeaderV1
compressionLatency : Compressor::Perfect
compressions : Compressor::Base::BaseStats
compressionSize : Compressor::Base::BaseStats
compressionSizeBits : Compressor::Base::BaseStats
compressor : BaseCache , Compressor::Base::BaseStats , Compressor::BaseDictionaryCompressor::DictionaryStats , Compressor::Multi::MultiStats
compressors : Compressor::Multi
compute_pgm_rsrc1_reserved : AMDKernelCode
compute_pgm_rsrc2_reserved : AMDKernelCode
compute_tmpring_size_pad : _amd_queue_s
compute_tmpring_size_waves : _amd_queue_s
compute_tmpring_size_wavesize : _amd_queue_s
computeIndices : TAGEBase::ThreadHistory
computeTags : TAGEBase::ThreadHistory
computeUnit : AtomicOpCAS< T > , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::ScalarDataPort , ComputeUnit::ScalarDTLBPort , ComputeUnit::SQCPort , ExecStage , FetchStage , FetchUnit , GlobalMemPipeline , LocalMemPipeline , RegisterFile , RegisterManager , ScalarMemPipeline , ScheduleStage , ScoreboardCheckStage , Wavefront
cond : ArmISA::FpRegRegRegCondOp , TimingExprIf
COND_DBG_SYS : Gcn3ISA::StatusReg
COND_DBG_USER : Gcn3ISA::StatusReg
condBranch : MultiperspectivePerceptron::MPPBranchInfo , TAGEBase::BranchInfo
condCode : ArmISA::BranchImmCond64 , ArmISA::DataXCondCompImmOp , ArmISA::DataXCondCompRegOp , ArmISA::DataXCondSelOp , ArmISA::FpCondCompRegOp , ArmISA::FpCondSelOp , ArmISA::PredOp
condIncorrect : BPredUnit::BPredUnitStats
conditional : ArmISA::SveSelectOp
condPredicted : BPredUnit::BPredUnitStats
conf : ArmISA::BrkPoint , ArmISA::SoftwareStep , ArmISA::VectorCatch , ArmISA::WatchPoint
confBase : GenericPciHost
confDeviceBits : GenericPciHost
confidence : LoopPredictor::LoopEntry , Prefetcher::SignaturePathV2::GlobalHistoryEntry , Prefetcher::Stride::StrideEntry
confidenceThreshold : LoopPredictor
config : dp_regs , PciDevice
Config : Sinic::Device
config : StreamTableEntry , VirtIO9PBase , VirtIOBlock , VirtIOConsole
configAddress : X86ISA::GpuTLB , X86ISA::TLB
configCache : SMMUv3
configCacheEnable : SMMUv3
configDelay : PciDevice
configFile : CxxConfigManager , TrafficGen
configLat : SMMUv3
configManager : CxxConfigManager::SimObjectResolver
configSem : SMMUv3
configSize : VirtIODeviceBase
configurations : FaultModel
conflictingLoads : MemDepUnit< MemDepPred, Impl >
conflictingStores : MemDepUnit< MemDepPred, Impl >
confSize : GenericPciHost
confTableReported : AbstractMemory , BackingStoreEntry
ConnectEvent : BaseRemoteGDB
connectEvent : BaseRemoteGDB
ConstPlainType : sc_core::sc_vector_iter< Element, AccessPolicy >
ConstT : RefCountingPtr< T >
consumerInst : DefaultIEW< Impl >
cont : cp::Print , StreamTableEntry
container : VecLaneT< VecElem, Const > , VecPredRegContainer< NumBits, Packed > , VecPredRegT< VecElem, NumElems, Packed, Const > , VecRegContainer< SIZE > , VecRegT< VecElem, NumElems, Const >
content_ptr : kfd_ioctl_dbg_address_watch_args , kfd_ioctl_dbg_wave_control_args
context : SMMUTranslationProcess , System::Threads::Thread , Wavefront
contextId : CacheBlk::Lock , LockedAddr , SparcISA::TlbRange
contextIds : Process
control : A9GlobalTimer::Timer , Pl011 , Sp804::Timer
control_directives : AMDKernelCode
controlFlowDivergenceDist : ComputeUnit
controlledDomain : PowerState
controller : AbstractController::MemoryPort
controlMispred : DefaultDecode< Impl >::DecodeStats
controlPage : UFSHostDevice::UFSSCSIDevice
controlPort : SMMUv3
conv : HDLcd
converter : Pl111
copiesProcessed : CopyEngine
coProcID : MipsISA::CoprocessorUnusableFault
copyBuffer : CopyEngine::CopyEngineChannel
CoreCount : FastModel::ScxEvsCortexA76< Types > , FastModel::ScxEvsCortexA76x1Types , FastModel::ScxEvsCortexA76x2Types , FastModel::ScxEvsCortexA76x3Types , FastModel::ScxEvsCortexA76x4Types
corePwrStatus : FVPBasePwrCtrl
cores : FastModel::CortexA76Cluster
coro : m5::Coroutine< Arg, Ret >::CallerType
coroutine : ItsProcess , SMMUProcess
correct : LoopPredictor::LoopPredictorStats , StatisticalCorrector::StatisticalCorrectorStats
count : ArmISA::ArmFault::FaultVals , DmaCallback , fun , InstructionQueue< Impl > , ProfileNode , RefCounted , sc_gem5::ReportMsgInfo , sc_gem5::ReportSevInfo , SimPoint::BBInfo , SMMUSemaphore , SparcISA::SparcFaultBase::FaultVals , TreePLRURP
counter : Intel8254Timer , Intel8254Timer::Counter::CounterEvent , Prefetcher::IrregularStreamBuffer::AddressMapping , Prefetcher::SignaturePath::PatternEntry , Prefetcher::SignaturePath::PatternStrideEntry , Prefetcher::STeMS::ActiveGenerationTableEntry::SequenceEntry , SatCounter
COUNTER_CTRL_CNTCV_HI : GenericTimerMem
COUNTER_CTRL_CNTCV_LO : GenericTimerMem
COUNTER_CTRL_CNTFID : GenericTimerMem
COUNTER_CTRL_CNTID : GenericTimerMem
COUNTER_CTRL_CNTSCR : GenericTimerMem
COUNTER_CTRL_CNTSR : GenericTimerMem
COUNTER_STATUS_CNTCV_HI : GenericTimerMem
COUNTER_STATUS_CNTCV_LO : GenericTimerMem
counterCtrlRange : GenericTimerMem
counterId : ArmISA::PMU::CounterState
counters : ArmISA::PMU
counterStatusRange : GenericTimerMem
countInt : UFSHostDevice
countNumSeqPkts : DramGen , HybridGen , NvmGen
countPages : ComputeUnit
counts : sc_gem5::UniqueNameGen
CP0_Config : MipsISA::CoreSpecific
CP0_Config1 : MipsISA::CoreSpecific
CP0_Config1_C2 : MipsISA::CoreSpecific
CP0_Config1_CA : MipsISA::CoreSpecific
CP0_Config1_DA : MipsISA::CoreSpecific
CP0_Config1_DL : MipsISA::CoreSpecific
CP0_Config1_DS : MipsISA::CoreSpecific
CP0_Config1_EP : MipsISA::CoreSpecific
CP0_Config1_FP : MipsISA::CoreSpecific
CP0_Config1_IA : MipsISA::CoreSpecific
CP0_Config1_IL : MipsISA::CoreSpecific
CP0_Config1_IS : MipsISA::CoreSpecific
CP0_Config1_M : MipsISA::CoreSpecific
CP0_Config1_MD : MipsISA::CoreSpecific
CP0_Config1_MMU : MipsISA::CoreSpecific
CP0_Config1_PC : MipsISA::CoreSpecific
CP0_Config1_WR : MipsISA::CoreSpecific
CP0_Config2 : MipsISA::CoreSpecific
CP0_Config2_M : MipsISA::CoreSpecific
CP0_Config2_SA : MipsISA::CoreSpecific
CP0_Config2_SL : MipsISA::CoreSpecific
CP0_Config2_SS : MipsISA::CoreSpecific
CP0_Config2_SU : MipsISA::CoreSpecific
CP0_Config2_TA : MipsISA::CoreSpecific
CP0_Config2_TL : MipsISA::CoreSpecific
CP0_Config2_TS : MipsISA::CoreSpecific
CP0_Config2_TU : MipsISA::CoreSpecific
CP0_Config3 : MipsISA::CoreSpecific
CP0_Config3_DSPP : MipsISA::CoreSpecific
CP0_Config3_LPA : MipsISA::CoreSpecific
CP0_Config3_M : MipsISA::CoreSpecific
CP0_Config3_MT : MipsISA::CoreSpecific
CP0_Config3_SM : MipsISA::CoreSpecific
CP0_Config3_SP : MipsISA::CoreSpecific
CP0_Config3_TL : MipsISA::CoreSpecific
CP0_Config3_VEIC : MipsISA::CoreSpecific
CP0_Config3_VInt : MipsISA::CoreSpecific
CP0_Config_AR : MipsISA::CoreSpecific
CP0_Config_AT : MipsISA::CoreSpecific
CP0_Config_BE : MipsISA::CoreSpecific
CP0_Config_MT : MipsISA::CoreSpecific
CP0_Config_VI : MipsISA::CoreSpecific
CP0_EBase_CPUNum : MipsISA::CoreSpecific
CP0_IntCtl_IPPCI : MipsISA::CoreSpecific
CP0_IntCtl_IPTI : MipsISA::CoreSpecific
CP0_PerfCtr_M : MipsISA::CoreSpecific
CP0_PerfCtr_W : MipsISA::CoreSpecific
CP0_PRId : MipsISA::CoreSpecific
CP0_PRId_CompanyID : MipsISA::CoreSpecific
CP0_PRId_CompanyOptions : MipsISA::CoreSpecific
CP0_PRId_ProcessorID : MipsISA::CoreSpecific
CP0_PRId_Revision : MipsISA::CoreSpecific
CP0_SrsCtl_HSS : MipsISA::CoreSpecific
CP0_WatchHi_M : MipsISA::CoreSpecific
cp0Updated : MipsISA::ISA
cp_seq : Trace::InstRecord
cp_seq_valid : Trace::InstRecord
CPBR : VGic
cpi : FullO3CPU< Impl > , Minor::MinorStats , TraceCPU::TraceStats
cpl : Pl111
cpsr : ArmISA::RemoteGDB::AArch32GdbRegCache , ArmISA::RemoteGDB::AArch64GdbRegCache , ArmISA::TableWalker::WalkerState , ArmISA::TLB
cpsrD : ArmISA::SoftwareStep
cpu : AtomicSimpleCPU::AtomicCPUDPort , BaseDynInst< Impl > , BaseKvmCPU::KVMCpuPort , CPUProgressEvent , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , ElasticTrace , GenericTimerISA , InstructionQueue< Impl > , Iob::IntMan , LSQ< Impl > , LSQ< Impl >::DcachePort , LSQUnit< Impl > , Minor::Decode , Minor::ExecContext , Minor::Execute , Minor::Fetch1 , Minor::Fetch2 , Minor::LSQ , Minor::Pipeline , MinorCPU::MinorCPUPort , O3ThreadContext< Impl > , O3ThreadState< Impl > , ROB< Impl > , SimpleExecContext , TimingSimpleCPU::FetchTranslation , TimingSimpleCPU::IprEvent , TimingSimpleCPU::TimingCPUPort , TimingSimpleCPU::TimingCPUPort::TickEvent
cpu_clock_counter : kfd_ioctl_get_clock_counters_args
CPU_Exit_Pri : EventBase
cpu_id : GicV2
cpu_list : GicV2
CPU_MAX : GicV2
cpu_mondo_head : SparcISA::ISA
cpu_mondo_tail : SparcISA::ISA
cpu_side_port : SerialLink , SerialLink::SerialLinkRequestPort
CPU_Switch_Pri : EventBase
CPU_Tick_Pri : EventBase
cpuBpr : GicV2
cpuClock : MipsAccess
cpuControl : GicV2
cpuFlags : X86ISA::IntelMP::Processor
cpuHighestInt : GicV2
cpuId : Gicv3CPUInterface , Gicv3Redistributor , Trace::TarmacParser
CpuID : VGic
cpuInterface : Gicv3Redistributor
cpuInterfaces : Gicv3
cpuIntrEnable : Sinic::Base
cpuList : BaseCPU
cpuName : Trace::TarmacTracerRecordV8::TraceEntryV8
cpuPendingIntr : NSGigE , Sinic::Base
cpuPioDelay : GicV2
cpuPointer : Shader
cpuPorts : SimpleCache
cpuPpiActive : GicV2
cpuPpiPending : GicV2
cpuPriority : GicV2
cpuRange : GicV2 , KvmKernelGicV2
cpuSgiActive : GicV2
cpuSgiActiveExt : GicV2
cpuSgiPending : GicV2
cpuSgiPendingExt : GicV2
cpuSidePort : AddrMapper , BaseCache , Bridge::BridgeRequestPort , Bridge , CoherentXBar::SnoopRespPort , CommMonitor , MemCheckerMonitor , RespPacketQueue , TLBCoalescer , X86ISA::GpuTLB
cpuSidePorts : BaseXBar , SnoopFilter
cpuSignature : X86ISA::IntelMP::Processor
cpuStack : MipsAccess
cpuTarget : GicV2
cpuThread : Shader
cpuWaitList : FullO3CPU< Impl >
cr : CopyEngine::CopyEngineChannel , PowerISA::RemoteGDB::PowerGdbRegCache
cr0 : SMMURegs
cr0ack : SMMURegs
cr1 : SMMURegs
cr2 : SMMURegs
CRDD : NSGigE
creatorID : X86ISA::ACPI::SysDescTable
creatorRevision : X86ISA::ACPI::SysDescTable
creditQueue : InputUnit
crossbarSwitch : Router
CrsrImage : Pl111
CrsrImageSize : Pl111
cs : X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED , X86ISA::RemoteGDB::X86GdbRegCache
csr : RiscvISA::CSROp , SparcISA::RemoteGDB::SPARCGdbRegCache
csum : iGbReg::RxDesc
ct0 : TAGEBase::BranchInfo
ct1 : TAGEBase::BranchInfo
CTDD : NSGigE
ctidbgirq : FastModel::ScxEvsCortexA76< Types >
ctl_stack_size : kfd_ioctl_create_queue_args
CTLR_QUIESCENT : Gicv3Its
ctr : PowerISA::RemoteGDB::PowerGdbRegCache , TAGEBase::TageEntry
ctrInsts : BaseKvmCPU
ctrl : CopyEngineReg::ChanRegs , IdeDisk , iGbReg::Regs , MemCtrl::CtrlStats , MemCtrl::MemoryPort , MemInterface , QoSMemSinkInterface
ctrl32 : FXSave
ctrl64 : FXSave
ctrl_ext : iGbReg::Regs
ctrlOffset : IdeController
ctrlRegIndex : ArmISA::BrkPoint , ArmISA::WatchPoint
ctx : Fiber , sc_gem5::Thread
ctx_save_restore_address : kfd_ioctl_create_queue_args
ctx_save_restore_size : kfd_ioctl_create_queue_args
cu : GPUExecContext , RegisterManagerPolicy
cu_id : ComputeUnit , GPUDynInst
cu_mask_ptr : kfd_ioctl_set_cu_mask_args
cuList : Shader
cuPort : LdsState
curAddr : ChunkGenerator , Pl111
curDmaDesc : CopyEngine::CopyEngineChannel
curDoorbell : UFSHostDevice::UFSHostDeviceStats
curFetching : IGbE::DescCache< T >
curMacroStaticInst : BaseSimpleCPU , CheckerCPU
curMsg : Trace::InstPBTrace
curPrd : IdeDisk
curPrdAddr : IdeDisk
curPrefixPtr : Packet::PrintReqState
currBit : I2CBus
currElement : TraceCPU::FixedRetryGen , TraceGen
currELHOffset : ArmISA::ArmFault::FaultVals
currELTOffset : ArmISA::ArmFault::FaultVals
current : Stats::AvgStor , Trace::ArmNativeTrace::ThreadState
currentBBV : SimPoint
currentBBVInstCount : SimPoint
currentDirectory : CheckpointIn
currentFunctionEnd : BaseCPU
currentFunctionStart : BaseCPU
currentIter : LoopPredictor::BranchInfo , LoopPredictor::LoopEntry
currentIterSpec : LoopPredictor::LoopEntry
currentProcess : sc_core::sc_sensitive
currentReadSSDQueue : UFSHostDevice::UFSHostDeviceStats
currentSCSIQueue : UFSHostDevice::UFSHostDeviceStats
currentTemp : ThermalDomain
currentWriteSSDQueue : UFSHostDevice::UFSHostDeviceStats
currRecordType : Trace::TarmacParserRecord
currState : ArmISA::TableWalker , TrafficGen
currStates : RiscvISA::Walker , X86ISA::Walker
curSector : IdeDisk , MmDisk
curSize : ChunkGenerator
cursorImage : Pl111
curState : VncServer
curStaticInst : BaseSimpleCPU , CheckerCPU
curThread : BaseSimpleCPU
curTime : MC146818
curTranType : ArmISA::TLB
cv : DistIface::Sync
cvec : Stats::DistData , Stats::DistStor , Stats::FormulaInfoProxy< Stat > , Stats::HistStor , Stats::Vector2dInfo , Stats::VectorInfoProxy< Stat >
cwp : SparcISA::ISA
cx_config : SparcISA::TLB
cx_tsb_ps0 : SparcISA::TLB
cx_tsb_ps1 : SparcISA::TLB
cycle : Clocked , instr
cycleCounter : ArmISA::PMU
cycleCounterEventId : ArmISA::PMU
cycles : DefaultFetch< Impl >::FetchStatGroup
cycleSem : SMMUv3
cyclesWaitingForDispatch : GPUDispatcher
cyl_high : CommandReg
cyl_low : CommandReg