utility.hh File Reference

#include "arch/arm/regs/cc.hh"
#include "arch/arm/regs/int.hh"
#include "arch/arm/regs/misc.hh"
#include "arch/arm/types.hh"
#include "base/logging.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"

Go to the source code of this file.

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
	gem5::ArmISA

Functions
bool	gem5::ArmISA::testPredicate (uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
void	gem5::ArmISA::sendEvent (ThreadContext *tc)
	Send an event (SEV) to a specific PE if there isn't already a pending event. More...
static bool	gem5::ArmISA::inUserMode (CPSR cpsr)
static bool	gem5::ArmISA::inPrivilegedMode (CPSR cpsr)
bool	gem5::ArmISA::isSecure (ThreadContext *tc)
bool	gem5::ArmISA::inAArch64 (ThreadContext *tc)
static OperatingMode	gem5::ArmISA::currOpMode (const ThreadContext *tc)
static ExceptionLevel	gem5::ArmISA::currEL (const ThreadContext *tc)
ExceptionLevel	gem5::ArmISA::currEL (CPSR cpsr)
bool	gem5::ArmISA::HavePACExt (ThreadContext *tc)
bool	gem5::ArmISA::HaveVirtHostExt (ThreadContext *tc)
bool	gem5::ArmISA::HaveLVA (ThreadContext *tc)
bool	gem5::ArmISA::HaveSecureEL2Ext (ThreadContext *tc)
bool	gem5::ArmISA::IsSecureEL2Enabled (ThreadContext *tc)
bool	gem5::ArmISA::EL2Enabled (ThreadContext *tc)
std::pair< bool, bool >	gem5::ArmISA::ELUsingAArch32K (ThreadContext *tc, ExceptionLevel el)
	This function checks whether selected EL provided as an argument is using the AArch32 ISA. More...
std::pair< bool, bool >	gem5::ArmISA::ELStateUsingAArch32K (ThreadContext *tc, ExceptionLevel el, bool secure)
bool	gem5::ArmISA::ELStateUsingAArch32 (ThreadContext *tc, ExceptionLevel el, bool secure)
bool	gem5::ArmISA::ELIs32 (ThreadContext *tc, ExceptionLevel el)
bool	gem5::ArmISA::ELIs64 (ThreadContext *tc, ExceptionLevel el)
bool	gem5::ArmISA::ELIsInHost (ThreadContext *tc, ExceptionLevel el)
	Returns true if the current exception level el is executing a Host OS or an application of a Host OS (Armv8.1 Virtualization Host Extensions). More...
ExceptionLevel	gem5::ArmISA::debugTargetFrom (ThreadContext *tc, bool secure)
bool	gem5::ArmISA::isBigEndian64 (const ThreadContext *tc)
bool	gem5::ArmISA::badMode32 (ThreadContext *tc, OperatingMode mode)
	badMode is checking if the execution mode provided as an argument is valid and implemented for AArch32 More...
bool	gem5::ArmISA::badMode (ThreadContext *tc, OperatingMode mode)
	badMode is checking if the execution mode provided as an argument is valid and implemented. More...
static uint8_t	gem5::ArmISA::itState (CPSR psr)
ExceptionLevel	gem5::ArmISA::s1TranslationRegime (ThreadContext *tc, ExceptionLevel el)
Addr	gem5::ArmISA::purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool isInstr)
	Removes the tag from tagged addresses if that mode is enabled. More...
Addr	gem5::ArmISA::purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, bool isInstr)
int	gem5::ArmISA::computeAddrTop (ThreadContext *tc, bool selbit, bool isInstr, TCR tcr, ExceptionLevel el)
static bool	gem5::ArmISA::inSecureState (SCR scr, CPSR cpsr)
bool	gem5::ArmISA::isSecureBelowEL3 (ThreadContext *tc)
bool	gem5::ArmISA::longDescFormatInUse (ThreadContext *tc)
RegVal	gem5::ArmISA::readMPIDR (ArmSystem *arm_sys, ThreadContext *tc)
	This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR), or it is issuing a read to VMPIDR_EL2 (as it happens in virtualized systems) More...
RegVal	gem5::ArmISA::getMPIDR (ArmSystem *arm_sys, ThreadContext *tc)
	This helper function is returning the value of MPIDR_EL1. More...
RegVal	gem5::ArmISA::getAffinity (ArmSystem *arm_sys, ThreadContext *tc)
	Retrieves MPIDR_EL1. More...
static uint32_t	gem5::ArmISA::mcrMrcIssBuild (bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn, uint32_t opc1, uint32_t opc2)
static void	gem5::ArmISA::mcrMrcIssExtract (uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
static uint32_t	gem5::ArmISA::mcrrMrrcIssBuild (bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2, uint32_t opc1)
static uint32_t	gem5::ArmISA::msrMrs64IssBuild (bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, IntRegIndex rt)
Fault	gem5::ArmISA::mcrMrc15Trap (const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm)
bool	gem5::ArmISA::mcrMrc15TrapToHyp (const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
bool	gem5::ArmISA::mcrMrc14TrapToHyp (const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
Fault	gem5::ArmISA::mcrrMrrc15Trap (const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm)
bool	gem5::ArmISA::mcrrMrrc15TrapToHyp (const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Fault	gem5::ArmISA::AArch64AArch32SystemAccessTrap (const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm, ExceptionClass ec)
bool	gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL1 (const MiscRegIndex miscReg, ThreadContext *tc)
bool	gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool	gem5::ArmISA::isGenericTimerHypTrap (const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
bool	gem5::ArmISA::condGenericTimerPhysHypTrap (const MiscRegIndex miscReg, ThreadContext *tc)
bool	gem5::ArmISA::isGenericTimerCommonEL0HypTrap (const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
bool	gem5::ArmISA::isGenericTimerPhysHypTrap (const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
bool	gem5::ArmISA::isGenericTimerSystemAccessTrapEL1 (const MiscRegIndex miscReg, ThreadContext *tc)
bool	gem5::ArmISA::condGenericTimerSystemAccessTrapEL1 (const MiscRegIndex miscReg, ThreadContext *tc)
bool	gem5::ArmISA::isGenericTimerSystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool	gem5::ArmISA::isGenericTimerCommonEL0SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool	gem5::ArmISA::isGenericTimerPhysEL0SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool	gem5::ArmISA::isGenericTimerPhysEL1SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool	gem5::ArmISA::isGenericTimerVirtSystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool	gem5::ArmISA::condGenericTimerCommonEL0SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool	gem5::ArmISA::condGenericTimerCommonEL1SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool	gem5::ArmISA::condGenericTimerPhysEL1SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
bool	gem5::ArmISA::isGenericTimerSystemAccessTrapEL3 (const MiscRegIndex miscReg, ThreadContext *tc)
bool	gem5::ArmISA::SPAlignmentCheckEnabled (ThreadContext *tc)
Addr	gem5::ArmISA::truncPage (Addr addr)
Addr	gem5::ArmISA::roundPage (Addr addr)
bool	gem5::ArmISA::decodeMrsMsrBankedReg (uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
static int	gem5::ArmISA::decodeMrsMsrBankedIntRegIndex (uint8_t sysM, bool r)
int	gem5::ArmISA::decodePhysAddrRange64 (uint8_t pa_enc)
	Returns the n. More...
uint8_t	gem5::ArmISA::encodePhysAddrRange64 (int pa_size)
	Returns the encoding corresponding to the specified n. More...
ByteOrder	gem5::ArmISA::byteOrder (const ThreadContext *tc)
bool	gem5::ArmISA::isUnpriviledgeAccess (ThreadContext *tc)