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gem5
v21.1.0.2
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gem5
v21.1.0.2
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This is the complete list of members for gem5::ArmISA::TLB, including all inherited members.
| _attr | gem5::ArmISA::TLB | protected |
| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool ignore_asn, ExceptionLevel target_el, bool in_host) | gem5::ArmISA::TLB | private |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| aarch64 | gem5::ArmISA::TLB | protected |
| aarch64EL | gem5::ArmISA::TLB | protected |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| AlignByte enum value | gem5::ArmISA::TLB | |
| AlignDoubleWord enum value | gem5::ArmISA::TLB | |
| AlignHalfWord enum value | gem5::ArmISA::TLB | |
| AlignmentMask enum value | gem5::ArmISA::TLB | |
| AlignOctWord enum value | gem5::ArmISA::TLB | |
| AlignQuadWord enum value | gem5::ArmISA::TLB | |
| AlignWord enum value | gem5::ArmISA::TLB | |
| AllowUnaligned enum value | gem5::ArmISA::TLB | |
| ArmFlags enum name | gem5::ArmISA::TLB | |
| ArmTranslationType enum name | gem5::ArmISA::TLB | |
| asid | gem5::ArmISA::TLB | protected |
| BaseTLB(const Params &p) | gem5::BaseTLB | inlineprotected |
| checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, BaseMMU::Mode mode, const bool is_priv) | gem5::ArmISA::TLB | |
| checkPermissions(TlbEntry *te, const RequestPtr &req, BaseMMU::Mode mode) | gem5::ArmISA::TLB | |
| checkPermissions64(TlbEntry *te, const RequestPtr &req, BaseMMU::Mode mode, ThreadContext *tc) | gem5::ArmISA::TLB | |
| cpsr | gem5::ArmISA::TLB | protected |
| currentSection() | gem5::Serializable | static |
| curTranType | gem5::ArmISA::TLB | protected |
| dacr | gem5::ArmISA::TLB | protected |
| demapPage(Addr vaddr, uint64_t asn) override | gem5::ArmISA::TLB | inlinevirtual |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| directToStage2 | gem5::ArmISA::TLB | protected |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() override | gem5::ArmISA::TLB | virtual |
| drainState() const | gem5::Drainable | inline |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const override | gem5::ArmISA::TLB | virtual |
| find(const char *name) | gem5::SimObject | static |
| flush(const TLBIALL &tlbi_op) | gem5::ArmISA::TLB | |
| flush(const TLBIALLEL &tlbi_op) | gem5::ArmISA::TLB | |
| flush(const TLBIVMALL &tlbi_op) | gem5::ArmISA::TLB | |
| flush(const TLBIALLN &tlbi_op) | gem5::ArmISA::TLB | |
| flush(const TLBIMVA &tlbi_op) | gem5::ArmISA::TLB | |
| flush(const TLBIASID &tlbi_op) | gem5::ArmISA::TLB | |
| flush(const TLBIMVAA &tlbi_op) | gem5::ArmISA::TLB | |
| flushAll() override | gem5::ArmISA::TLB | virtual |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getAttr() const | gem5::ArmISA::TLB | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) | gem5::SimObject | virtual |
| getProbeManager() | gem5::SimObject | |
| getResultTe(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool timing, bool functional, TlbEntry *mergeTe) | gem5::ArmISA::TLB | |
| getSimObjectResolver() | gem5::SimObject | static |
| getsize() const | gem5::ArmISA::TLB | inline |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| getTableWalker() | gem5::ArmISA::TLB | inline |
| getTableWalkerPort() override | gem5::ArmISA::TLB | virtual |
| getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool timing, bool functional, bool is_secure, ArmTranslationType tranType) | gem5::ArmISA::TLB | |
| getVMID(ThreadContext *tc) const | gem5::ArmISA::TLB | protected |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| haveLargeAsid64 | gem5::ArmISA::TLB | protected |
| haveLPAE | gem5::ArmISA::TLB | protected |
| haveVirtualization | gem5::ArmISA::TLB | protected |
| hcr | gem5::ArmISA::TLB | protected |
| HypMode enum value | gem5::ArmISA::TLB | |
| init() | gem5::SimObject | virtual |
| initState() | gem5::SimObject | virtual |
| insert(Addr vaddr, TlbEntry &pte) | gem5::ArmISA::TLB | |
| invalidateMiscReg() | gem5::ArmISA::TLB | inline |
| isHyp | gem5::ArmISA::TLB | protected |
| isPriv | gem5::ArmISA::TLB | protected |
| isSecure | gem5::ArmISA::TLB | protected |
| isStage2 | gem5::ArmISA::TLB | protected |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| lookup(Addr vpn, uint16_t asn, vmid_t vmid, bool hyp, bool secure, bool functional, bool ignore_asn, ExceptionLevel target_el, bool in_host, BaseMMU::Mode mode) | gem5::ArmISA::TLB | |
| m5opRange | gem5::ArmISA::TLB | protected |
| memInvalidate() | gem5::BaseTLB | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| miscRegContext | gem5::ArmISA::TLB | protected |
| miscRegValid | gem5::ArmISA::TLB | protected |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nmrr | gem5::ArmISA::TLB | protected |
| NormalTran enum value | gem5::ArmISA::TLB | |
| notifyFork() | gem5::Drainable | inlinevirtual |
| operator=(const Group &)=delete | gem5::statistics::Group | |
| Params typedef | gem5::ArmISA::TLB | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| physAddrRange | gem5::ArmISA::TLB | protected |
| ppRefills | gem5::ArmISA::TLB | protected |
| preDumpStats() | gem5::statistics::Group | virtual |
| printTlb() const | gem5::ArmISA::TLB | |
| probeManager | gem5::SimObject | private |
| prrr | gem5::ArmISA::TLB | protected |
| rangeMRU | gem5::ArmISA::TLB | protected |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() override | gem5::ArmISA::TLB | virtual |
| regStats() | gem5::statistics::Group | virtual |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| S12E0Tran enum value | gem5::ArmISA::TLB | |
| S12E1Tran enum value | gem5::ArmISA::TLB | |
| S1CTran enum value | gem5::ArmISA::TLB | |
| S1E0Tran enum value | gem5::ArmISA::TLB | |
| S1E1Tran enum value | gem5::ArmISA::TLB | |
| S1E2Tran enum value | gem5::ArmISA::TLB | |
| S1E3Tran enum value | gem5::ArmISA::TLB | |
| S1S2NsTran enum value | gem5::ArmISA::TLB | |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| scr | gem5::ArmISA::TLB | protected |
| sctlr | gem5::ArmISA::TLB | protected |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::SimObject | inlinevirtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setAttr(uint64_t attr) | gem5::ArmISA::TLB | inline |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| setStage2Tlb(TLB *stage2_tlb) | gem5::ArmISA::TLB | inline |
| setTableWalker(TableWalker *table_walker) | gem5::ArmISA::TLB | |
| setTestInterface(SimObject *ti) | gem5::ArmISA::TLB | |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| simObjectList | gem5::SimObject | privatestatic |
| SimObjectList typedef | gem5::SimObject | private |
| size | gem5::ArmISA::TLB | protected |
| stage2DescReq | gem5::ArmISA::TLB | protected |
| stage2Req | gem5::ArmISA::TLB | protected |
| stage2Tlb | gem5::ArmISA::TLB | protected |
| startup() | gem5::SimObject | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::ArmISA::TLB | protected |
| table | gem5::ArmISA::TLB | protected |
| tableWalker | gem5::ArmISA::TLB | protected |
| takeOverFrom(BaseTLB *otlb) override | gem5::ArmISA::TLB | virtual |
| test | gem5::ArmISA::TLB | protected |
| testTranslation(const RequestPtr &req, BaseMMU::Mode mode, TlbEntry::DomainType domain) | gem5::ArmISA::TLB | |
| testWalk(Addr pa, Addr size, Addr va, bool is_secure, BaseMMU::Mode mode, TlbEntry::DomainType domain, LookupLevel lookup_level) | gem5::ArmISA::TLB | |
| TLB(const Params &p) | gem5::ArmISA::TLB | |
| TLB(const Params &p, int _size, TableWalker *_walker) | gem5::ArmISA::TLB | |
| translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tranType) | gem5::ArmISA::TLB | |
| translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override | gem5::ArmISA::TLB | inlinevirtual |
| translateComplete(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, ArmTranslationType tranType, bool callFromS2) | gem5::ArmISA::TLB | |
| translateFs(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool &delay, bool timing, ArmTranslationType tranType, bool functional=false) | gem5::ArmISA::TLB | |
| translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr) | gem5::ArmISA::TLB | |
| translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, ArmTranslationType tranType) | gem5::ArmISA::TLB | |
| translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) override | gem5::ArmISA::TLB | inlinevirtual |
| translateMmuOff(ThreadContext *tc, const RequestPtr &req, BaseMMU::Mode mode, TLB::ArmTranslationType tranType, Addr vaddr, bool long_desc_format) | gem5::ArmISA::TLB | |
| translateMmuOn(ThreadContext *tc, const RequestPtr &req, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool &delay, bool timing, bool functional, Addr vaddr, ArmFault::TranMethod tranMethod) | gem5::ArmISA::TLB | |
| translateSe(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode, BaseMMU::Translation *translation, bool &delay, bool timing) | gem5::ArmISA::TLB | |
| translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode, ArmTranslationType tranType) | gem5::ArmISA::TLB | |
| translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode) override | gem5::ArmISA::TLB | inlinevirtual |
| tranTypeEL(CPSR cpsr, ArmTranslationType type) | gem5::ArmISA::TLB | static |
| trickBoxCheck(const RequestPtr &req, BaseMMU::Mode mode, TlbEntry::DomainType domain) | gem5::ArmISA::TLB | |
| ttbcr | gem5::ArmISA::TLB | protected |
| unserialize(CheckpointIn &cp) override | gem5::SimObject | inlinevirtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| updateMiscReg(ThreadContext *tc, ArmTranslationType tranType=NormalTran) | gem5::ArmISA::TLB | protected |
| UserMode enum value | gem5::ArmISA::TLB | |
| vmid | gem5::ArmISA::TLB | protected |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level) | gem5::ArmISA::TLB | |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |
| ~TLB() | gem5::ArmISA::TLB | virtual |