misc.hh File Reference

#include "arch/x86/regs/segment.hh"
#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
#include "base/logging.hh"

Go to the source code of this file.

Classes
class	gem5::X86ISA::SegDescriptorLimit

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
	gem5::X86ISA
	This is exposed globally, independent of the ISA.

Enumerations
enum	gem5::X86ISA::CondFlagBit {   gem5::X86ISA::CFBit = 1 << 0, gem5::X86ISA::PFBit = 1 << 2, gem5::X86ISA::ECFBit = 1 << 3, gem5::X86ISA::AFBit = 1 << 4,   gem5::X86ISA::EZFBit = 1 << 5, gem5::X86ISA::ZFBit = 1 << 6, gem5::X86ISA::SFBit = 1 << 7, gem5::X86ISA::DFBit = 1 << 10,   gem5::X86ISA::OFBit = 1 << 11 }
enum	gem5::X86ISA::RFLAGBit {   gem5::X86ISA::TFBit = 1 << 8, gem5::X86ISA::IFBit = 1 << 9, gem5::X86ISA::NTBit = 1 << 14, gem5::X86ISA::RFBit = 1 << 16,   gem5::X86ISA::VMBit = 1 << 17, gem5::X86ISA::ACBit = 1 << 18, gem5::X86ISA::VIFBit = 1 << 19, gem5::X86ISA::VIPBit = 1 << 20,   gem5::X86ISA::IDBit = 1 << 21 }
enum	gem5::X86ISA::X87StatusBit {   gem5::X86ISA::IEBit = 1 << 0, gem5::X86ISA::DEBit = 1 << 1, gem5::X86ISA::ZEBit = 1 << 2, gem5::X86ISA::OEBit = 1 << 3,   gem5::X86ISA::UEBit = 1 << 4, gem5::X86ISA::PEBit = 1 << 5, gem5::X86ISA::StackFaultBit = 1 << 6, gem5::X86ISA::ErrSummaryBit = 1 << 7,   gem5::X86ISA::CC0Bit = 1 << 8, gem5::X86ISA::CC1Bit = 1 << 9, gem5::X86ISA::CC2Bit = 1 << 10, gem5::X86ISA::CC3Bit = 1 << 14,   gem5::X86ISA::BusyBit = 1 << 15 }
enum	gem5::X86ISA::MiscRegIndex {   gem5::X86ISA::MISCREG_CR_BASE, gem5::X86ISA::MISCREG_CR0 = MISCREG_CR_BASE, gem5::X86ISA::MISCREG_CR1, gem5::X86ISA::MISCREG_CR2,   gem5::X86ISA::MISCREG_CR3, gem5::X86ISA::MISCREG_CR4, gem5::X86ISA::MISCREG_CR5, gem5::X86ISA::MISCREG_CR6,   gem5::X86ISA::MISCREG_CR7, gem5::X86ISA::MISCREG_CR8, gem5::X86ISA::MISCREG_CR9, gem5::X86ISA::MISCREG_CR10,   gem5::X86ISA::MISCREG_CR11, gem5::X86ISA::MISCREG_CR12, gem5::X86ISA::MISCREG_CR13, gem5::X86ISA::MISCREG_CR14,   gem5::X86ISA::MISCREG_CR15, gem5::X86ISA::MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, gem5::X86ISA::MISCREG_DR0 = MISCREG_DR_BASE, gem5::X86ISA::MISCREG_DR1,   gem5::X86ISA::MISCREG_DR2, gem5::X86ISA::MISCREG_DR3, gem5::X86ISA::MISCREG_DR4, gem5::X86ISA::MISCREG_DR5,   gem5::X86ISA::MISCREG_DR6, gem5::X86ISA::MISCREG_DR7, gem5::X86ISA::MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, gem5::X86ISA::MISCREG_M5_REG,   gem5::X86ISA::MISCREG_TSC, gem5::X86ISA::MISCREG_MTRRCAP, gem5::X86ISA::MISCREG_SYSENTER_CS, gem5::X86ISA::MISCREG_SYSENTER_ESP,   gem5::X86ISA::MISCREG_SYSENTER_EIP, gem5::X86ISA::MISCREG_MCG_CAP, gem5::X86ISA::MISCREG_MCG_STATUS, gem5::X86ISA::MISCREG_MCG_CTL,   gem5::X86ISA::MISCREG_DEBUG_CTL_MSR, gem5::X86ISA::MISCREG_LAST_BRANCH_FROM_IP, gem5::X86ISA::MISCREG_LAST_BRANCH_TO_IP, gem5::X86ISA::MISCREG_LAST_EXCEPTION_FROM_IP,   gem5::X86ISA::MISCREG_LAST_EXCEPTION_TO_IP, gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_BASE, gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_1,   gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_2, gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_3, gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_4, gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_5,   gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_6, gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_7, gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_END, gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END,   gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_1, gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_2, gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_3,   gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_4, gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_5, gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_6, gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_7,   gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_END, gem5::X86ISA::MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END, gem5::X86ISA::MISCREG_MTRR_FIX_16K_80000, gem5::X86ISA::MISCREG_MTRR_FIX_16K_A0000,   gem5::X86ISA::MISCREG_MTRR_FIX_4K_C0000, gem5::X86ISA::MISCREG_MTRR_FIX_4K_C8000, gem5::X86ISA::MISCREG_MTRR_FIX_4K_D0000, gem5::X86ISA::MISCREG_MTRR_FIX_4K_D8000,   gem5::X86ISA::MISCREG_MTRR_FIX_4K_E0000, gem5::X86ISA::MISCREG_MTRR_FIX_4K_E8000, gem5::X86ISA::MISCREG_MTRR_FIX_4K_F0000, gem5::X86ISA::MISCREG_MTRR_FIX_4K_F8000,   gem5::X86ISA::MISCREG_PAT, gem5::X86ISA::MISCREG_DEF_TYPE, gem5::X86ISA::MISCREG_MC_CTL_BASE, gem5::X86ISA::MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,   gem5::X86ISA::MISCREG_MC1_CTL, gem5::X86ISA::MISCREG_MC2_CTL, gem5::X86ISA::MISCREG_MC3_CTL, gem5::X86ISA::MISCREG_MC4_CTL,   gem5::X86ISA::MISCREG_MC5_CTL, gem5::X86ISA::MISCREG_MC6_CTL, gem5::X86ISA::MISCREG_MC7_CTL, gem5::X86ISA::MISCREG_MC_CTL_END,   gem5::X86ISA::MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END, gem5::X86ISA::MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, gem5::X86ISA::MISCREG_MC1_STATUS, gem5::X86ISA::MISCREG_MC2_STATUS,   gem5::X86ISA::MISCREG_MC3_STATUS, gem5::X86ISA::MISCREG_MC4_STATUS, gem5::X86ISA::MISCREG_MC5_STATUS, gem5::X86ISA::MISCREG_MC6_STATUS,   gem5::X86ISA::MISCREG_MC7_STATUS, gem5::X86ISA::MISCREG_MC_STATUS_END, gem5::X86ISA::MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END, gem5::X86ISA::MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,   gem5::X86ISA::MISCREG_MC1_ADDR, gem5::X86ISA::MISCREG_MC2_ADDR, gem5::X86ISA::MISCREG_MC3_ADDR, gem5::X86ISA::MISCREG_MC4_ADDR,   gem5::X86ISA::MISCREG_MC5_ADDR, gem5::X86ISA::MISCREG_MC6_ADDR, gem5::X86ISA::MISCREG_MC7_ADDR, gem5::X86ISA::MISCREG_MC_ADDR_END,   gem5::X86ISA::MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END, gem5::X86ISA::MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, gem5::X86ISA::MISCREG_MC1_MISC, gem5::X86ISA::MISCREG_MC2_MISC,   gem5::X86ISA::MISCREG_MC3_MISC, gem5::X86ISA::MISCREG_MC4_MISC, gem5::X86ISA::MISCREG_MC5_MISC, gem5::X86ISA::MISCREG_MC6_MISC,   gem5::X86ISA::MISCREG_MC7_MISC, gem5::X86ISA::MISCREG_MC_MISC_END, gem5::X86ISA::MISCREG_EFER = MISCREG_MC_MISC_END, gem5::X86ISA::MISCREG_STAR,   gem5::X86ISA::MISCREG_LSTAR, gem5::X86ISA::MISCREG_CSTAR, gem5::X86ISA::MISCREG_SF_MASK, gem5::X86ISA::MISCREG_KERNEL_GS_BASE,   gem5::X86ISA::MISCREG_TSC_AUX, gem5::X86ISA::MISCREG_PERF_EVT_SEL_BASE, gem5::X86ISA::MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, gem5::X86ISA::MISCREG_PERF_EVT_SEL1,   gem5::X86ISA::MISCREG_PERF_EVT_SEL2, gem5::X86ISA::MISCREG_PERF_EVT_SEL3, gem5::X86ISA::MISCREG_PERF_EVT_SEL_END, gem5::X86ISA::MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END,   gem5::X86ISA::MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, gem5::X86ISA::MISCREG_PERF_EVT_CTR1, gem5::X86ISA::MISCREG_PERF_EVT_CTR2, gem5::X86ISA::MISCREG_PERF_EVT_CTR3,   gem5::X86ISA::MISCREG_PERF_EVT_CTR_END, gem5::X86ISA::MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END, gem5::X86ISA::MISCREG_IORR_BASE_BASE, gem5::X86ISA::MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,   gem5::X86ISA::MISCREG_IORR_BASE1, gem5::X86ISA::MISCREG_IORR_BASE_END, gem5::X86ISA::MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END, gem5::X86ISA::MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,   gem5::X86ISA::MISCREG_IORR_MASK1, gem5::X86ISA::MISCREG_IORR_MASK_END, gem5::X86ISA::MISCREG_TOP_MEM = MISCREG_IORR_MASK_END, gem5::X86ISA::MISCREG_TOP_MEM2,   gem5::X86ISA::MISCREG_VM_CR, gem5::X86ISA::MISCREG_IGNNE, gem5::X86ISA::MISCREG_SMM_CTL, gem5::X86ISA::MISCREG_VM_HSAVE_PA,   gem5::X86ISA::MISCREG_SEG_SEL_BASE, gem5::X86ISA::MISCREG_ES = MISCREG_SEG_SEL_BASE, gem5::X86ISA::MISCREG_CS, gem5::X86ISA::MISCREG_SS,   gem5::X86ISA::MISCREG_DS, gem5::X86ISA::MISCREG_FS, gem5::X86ISA::MISCREG_GS, gem5::X86ISA::MISCREG_HS,   gem5::X86ISA::MISCREG_TSL, gem5::X86ISA::MISCREG_TSG, gem5::X86ISA::MISCREG_LS, gem5::X86ISA::MISCREG_MS,   gem5::X86ISA::MISCREG_TR, gem5::X86ISA::MISCREG_IDTR, gem5::X86ISA::MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS, gem5::X86ISA::MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,   gem5::X86ISA::MISCREG_CS_BASE, gem5::X86ISA::MISCREG_SS_BASE, gem5::X86ISA::MISCREG_DS_BASE, gem5::X86ISA::MISCREG_FS_BASE,   gem5::X86ISA::MISCREG_GS_BASE, gem5::X86ISA::MISCREG_HS_BASE, gem5::X86ISA::MISCREG_TSL_BASE, gem5::X86ISA::MISCREG_TSG_BASE,   gem5::X86ISA::MISCREG_LS_BASE, gem5::X86ISA::MISCREG_MS_BASE, gem5::X86ISA::MISCREG_TR_BASE, gem5::X86ISA::MISCREG_IDTR_BASE,   gem5::X86ISA::MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS, gem5::X86ISA::MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE, gem5::X86ISA::MISCREG_CS_EFF_BASE, gem5::X86ISA::MISCREG_SS_EFF_BASE,   gem5::X86ISA::MISCREG_DS_EFF_BASE, gem5::X86ISA::MISCREG_FS_EFF_BASE, gem5::X86ISA::MISCREG_GS_EFF_BASE, gem5::X86ISA::MISCREG_HS_EFF_BASE,   gem5::X86ISA::MISCREG_TSL_EFF_BASE, gem5::X86ISA::MISCREG_TSG_EFF_BASE, gem5::X86ISA::MISCREG_LS_EFF_BASE, gem5::X86ISA::MISCREG_MS_EFF_BASE,   gem5::X86ISA::MISCREG_TR_EFF_BASE, gem5::X86ISA::MISCREG_IDTR_EFF_BASE, gem5::X86ISA::MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS, gem5::X86ISA::MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,   gem5::X86ISA::MISCREG_CS_LIMIT, gem5::X86ISA::MISCREG_SS_LIMIT, gem5::X86ISA::MISCREG_DS_LIMIT, gem5::X86ISA::MISCREG_FS_LIMIT,   gem5::X86ISA::MISCREG_GS_LIMIT, gem5::X86ISA::MISCREG_HS_LIMIT, gem5::X86ISA::MISCREG_TSL_LIMIT, gem5::X86ISA::MISCREG_TSG_LIMIT,   gem5::X86ISA::MISCREG_LS_LIMIT, gem5::X86ISA::MISCREG_MS_LIMIT, gem5::X86ISA::MISCREG_TR_LIMIT, gem5::X86ISA::MISCREG_IDTR_LIMIT,   gem5::X86ISA::MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS, gem5::X86ISA::MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, gem5::X86ISA::MISCREG_CS_ATTR, gem5::X86ISA::MISCREG_SS_ATTR,   gem5::X86ISA::MISCREG_DS_ATTR, gem5::X86ISA::MISCREG_FS_ATTR, gem5::X86ISA::MISCREG_GS_ATTR, gem5::X86ISA::MISCREG_HS_ATTR,   gem5::X86ISA::MISCREG_TSL_ATTR, gem5::X86ISA::MISCREG_TSG_ATTR, gem5::X86ISA::MISCREG_LS_ATTR, gem5::X86ISA::MISCREG_MS_ATTR,   gem5::X86ISA::MISCREG_TR_ATTR, gem5::X86ISA::MISCREG_IDTR_ATTR, gem5::X86ISA::MISCREG_X87_TOP, gem5::X86ISA::MISCREG_MXCSR,   gem5::X86ISA::MISCREG_FCW, gem5::X86ISA::MISCREG_FSW, gem5::X86ISA::MISCREG_FTW, gem5::X86ISA::MISCREG_FTAG,   gem5::X86ISA::MISCREG_FISEG, gem5::X86ISA::MISCREG_FIOFF, gem5::X86ISA::MISCREG_FOSEG, gem5::X86ISA::MISCREG_FOOFF,   gem5::X86ISA::MISCREG_FOP, gem5::X86ISA::MISCREG_APIC_BASE, gem5::X86ISA::MISCREG_PCI_CONFIG_ADDRESS, gem5::X86ISA::NUM_MISCREGS }

Functions
static bool	gem5::X86ISA::isValidMiscReg (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_CR (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_DR (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_MTRR_PHYS_BASE (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_MTRR_PHYS_MASK (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_MC_CTL (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_MC_STATUS (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_MC_ADDR (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_MC_MISC (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_PERF_EVT_SEL (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_PERF_EVT_CTR (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_IORR_BASE (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_IORR_MASK (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_SEG_SEL (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_SEG_BASE (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_SEG_EFF_BASE (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_SEG_LIMIT (int index)
static MiscRegIndex	gem5::X86ISA::MISCREG_SEG_ATTR (int index)
	gem5::X86ISA::BitUnion64 (CCFlagBits) Bitfield< 11 > of
	A type to describe the condition code bits of the RFLAGS register, plus two flags, EZF and ECF, which are only visible to microcode. More...
	gem5::X86ISA::EndBitUnion (CCFlagBits) BitUnion64(RFLAGS) Bitfield< 21 > id
	RFLAGS. More...
	gem5::X86ISA::EndBitUnion (RFLAGS) BitUnion64(HandyM5Reg) Bitfield< 0 > mode
	gem5::X86ISA::EndBitUnion (HandyM5Reg) BitUnion64(CR0) Bitfield< 31 > pg
	Control registers. More...
	gem5::X86ISA::EndBitUnion (CR0) BitUnion64(CR2) Bitfield< 31
	gem5::X86ISA::EndBitUnion (CR2) BitUnion64(CR3) Bitfield< 51
	gem5::X86ISA::EndBitUnion (CR3) BitUnion64(CR4) Bitfield< 18 > osxsave
	gem5::X86ISA::EndBitUnion (CR4) BitUnion64(CR8) Bitfield< 3
	gem5::X86ISA::EndBitUnion (CR8) BitUnion64(DR6) Bitfield< 0 > b0
	gem5::X86ISA::EndBitUnion (DR6) BitUnion64(DR7) Bitfield< 0 > l0
	gem5::X86ISA::EndBitUnion (DR7) BitUnion64(MTRRcap) Bitfield< 7
	gem5::X86ISA::EndBitUnion (MTRRcap) BitUnion64(SysenterCS) Bitfield< 15
	SYSENTER configuration registers. More...
	gem5::X86ISA::EndBitUnion (SysenterCS) BitUnion64(SysenterESP) Bitfield< 31
	gem5::X86ISA::EndBitUnion (SysenterESP) BitUnion64(SysenterEIP) Bitfield< 31
	gem5::X86ISA::EndBitUnion (SysenterEIP) BitUnion64(McgCap) Bitfield< 7
	Global machine check registers. More...
	gem5::X86ISA::EndBitUnion (McgCap) BitUnion64(McgStatus) Bitfield< 0 > ripv
	gem5::X86ISA::EndBitUnion (McgStatus) BitUnion64(DebugCtlMsr) Bitfield< 0 > lbr
	gem5::X86ISA::EndBitUnion (DebugCtlMsr) BitUnion64(MtrrPhysBase) Bitfield< 7
	gem5::X86ISA::EndBitUnion (MtrrPhysBase) BitUnion64(MtrrPhysMask) Bitfield< 11 > valid
	gem5::X86ISA::EndBitUnion (MtrrPhysMask) BitUnion64(MtrrFixed) EndBitUnion(MtrrFixed) BitUnion64(Pat) EndBitUnion(Pat) BitUnion64(MtrrDefType) Bitfield< 7
	gem5::X86ISA::EndBitUnion (MtrrDefType) BitUnion64(McStatus) Bitfield< 15
	Machine check. More...
	gem5::X86ISA::EndBitUnion (McStatus) BitUnion64(McCtl) EndBitUnion(McCtl) BitUnion64(Efer) Bitfield< 0 > sce
	gem5::X86ISA::EndBitUnion (Efer) BitUnion64(Star) Bitfield< 31
	gem5::X86ISA::EndBitUnion (Star) BitUnion64(SfMask) Bitfield< 31
	gem5::X86ISA::EndBitUnion (SfMask) BitUnion64(PerfEvtSel) Bitfield< 7
	gem5::X86ISA::EndBitUnion (PerfEvtSel) BitUnion32(Syscfg) Bitfield< 18 > mfde
	gem5::X86ISA::EndBitUnion (Syscfg) BitUnion64(IorrBase) Bitfield< 3 > wr
	gem5::X86ISA::EndBitUnion (IorrBase) BitUnion64(IorrMask) Bitfield< 11 > v
	gem5::X86ISA::EndBitUnion (IorrMask) BitUnion64(Tom) Bitfield< 51
	gem5::X86ISA::EndBitUnion (Tom) BitUnion64(VmCrMsr) Bitfield< 0 > dpd
	gem5::X86ISA::EndBitUnion (VmCrMsr) BitUnion64(IgnneMsr) Bitfield< 0 > ignne
	gem5::X86ISA::EndBitUnion (IgnneMsr) BitUnion64(SmmCtlMsr) Bitfield< 0 > dismiss
	gem5::X86ISA::EndBitUnion (SmmCtlMsr) BitUnion64(SegSelector) Bitfield< 63
	Segment Selector. More...
	gem5::X86ISA::EndBitUnion (SegSelector) class SegDescriptorBase
	Segment Descriptors. More...
	gem5::X86ISA::BitUnion64 (SegDescriptor) Bitfield< 63
	gem5::X86ISA::SubBitUnion (type, 43, 40) Bitfield< 43 > codeOrData
	gem5::X86ISA::EndSubBitUnion (type) EndBitUnion(SegDescriptor) BitUnion64(TSSlow) Bitfield< 63
	TSS Descriptor (long mode - 128 bits) the lower 64 bits. More...
	gem5::X86ISA::EndBitUnion (TSShigh) BitUnion64(SegAttr) Bitfield< 1
	gem5::X86ISA::EndBitUnion (SegAttr) BitUnion64(GateDescriptor) Bitfield< 63
	gem5::X86ISA::EndBitUnion (GateDescriptor) BitUnion64(GateDescriptorLow) Bitfield< 63
	Long Mode Gate Descriptor. More...
	gem5::X86ISA::EndBitUnion (GateDescriptorLow) BitUnion64(GateDescriptorHigh) Bitfield< 31
	gem5::X86ISA::EndBitUnion (GateDescriptorHigh) BitUnion64(GDTR) EndBitUnion(GDTR) BitUnion64(IDTR) EndBitUnion(IDTR) BitUnion64(LDTR) EndBitUnion(LDTR) BitUnion64(TR) EndBitUnion(TR) BitUnion64(LocalApicBase) Bitfield< 51
	Descriptor-Table Registers. More...

Variables
const uint32_t	gem5::X86ISA::cfofMask = CFBit | OFBit
const uint32_t	gem5::X86ISA::ccFlagMask = PFBit | AFBit | ZFBit | SFBit
Bitfield< 7 >	gem5::X86ISA::sf
Bitfield< 6 >	gem5::X86ISA::zf
Bitfield< 5 >	gem5::X86ISA::ezf
Bitfield< 4 >	gem5::X86ISA::af
Bitfield< 3 >	gem5::X86ISA::ecf
Bitfield< 2 >	gem5::X86ISA::pf
Bitfield< 0 >	gem5::X86ISA::cf
Bitfield< 20 >	gem5::X86ISA::vip
Bitfield< 19 >	gem5::X86ISA::vif
Bitfield< 18 >	gem5::X86ISA::ac
Bitfield< 17 >	gem5::X86ISA::vm
Bitfield< 16 >	gem5::X86ISA::rf
Bitfield< 14 >	gem5::X86ISA::nt
Bitfield< 13, 12 >	gem5::X86ISA::iopl
Bitfield< 11 >	gem5::X86ISA::of
Bitfield< 10 >	gem5::X86ISA::df
Bitfield< 9 >	gem5::X86ISA::intf
Bitfield< 8 >	gem5::X86ISA::tf
Bitfield< 3, 1 >	gem5::X86ISA::submode
Bitfield< 5, 4 >	gem5::X86ISA::cpl
Bitfield< 6 >	gem5::X86ISA::paging
Bitfield< 7 >	gem5::X86ISA::prot
Bitfield< 9, 8 >	gem5::X86ISA::defOp
Bitfield< 11, 10 >	gem5::X86ISA::altOp
Bitfield< 13, 12 >	gem5::X86ISA::defAddr
Bitfield< 15, 14 >	gem5::X86ISA::altAddr
Bitfield< 17, 16 >	gem5::X86ISA::stack
Bitfield< 30 >	gem5::X86ISA::cd
Bitfield< 29 >	gem5::X86ISA::nw
Bitfield< 18 >	gem5::X86ISA::am
Bitfield< 16 >	gem5::X86ISA::wp
Bitfield< 5 >	gem5::X86ISA::ne
Bitfield< 4 >	gem5::X86ISA::et
Bitfield< 3 >	gem5::X86ISA::ts
Bitfield< 2 >	gem5::X86ISA::em
Bitfield< 1 >	gem5::X86ISA::mp
Bitfield< 0 >	gem5::X86ISA::pe
	gem5::X86ISA::legacy
	gem5::X86ISA::longPdtb
Bitfield< 31, 12 >	gem5::X86ISA::pdtb
Bitfield< 31, 5 >	gem5::X86ISA::paePdtb
Bitfield< 16 >	gem5::X86ISA::fsgsbase
Bitfield< 10 >	gem5::X86ISA::osxmmexcpt
Bitfield< 9 >	gem5::X86ISA::osfxsr
Bitfield< 8 >	gem5::X86ISA::pce
Bitfield< 7 >	gem5::X86ISA::pge
Bitfield< 6 >	gem5::X86ISA::mce
Bitfield< 5 >	gem5::X86ISA::pae
Bitfield< 4 >	gem5::X86ISA::pse
Bitfield< 3 >	gem5::X86ISA::de
Bitfield< 2 >	gem5::X86ISA::tsd
Bitfield< 1 >	gem5::X86ISA::pvi
Bitfield< 0 >	gem5::X86ISA::vme
	gem5::X86ISA::tpr
Bitfield< 1 >	gem5::X86ISA::b1
Bitfield< 2 >	gem5::X86ISA::b2
Bitfield< 3 >	gem5::X86ISA::b3
Bitfield< 13 >	gem5::X86ISA::bd
Bitfield< 14 >	gem5::X86ISA::bs
Bitfield< 15 >	gem5::X86ISA::bt
Bitfield< 1 >	gem5::X86ISA::g0
Bitfield< 2 >	gem5::X86ISA::l1
Bitfield< 3 >	gem5::X86ISA::g1
Bitfield< 4 >	gem5::X86ISA::l2
Bitfield< 5 >	gem5::X86ISA::g2
Bitfield< 6 >	gem5::X86ISA::l3
Bitfield< 7 >	gem5::X86ISA::g3
Bitfield< 8 >	gem5::X86ISA::le
Bitfield< 9 >	gem5::X86ISA::ge
Bitfield< 13 >	gem5::X86ISA::gd
Bitfield< 17, 16 >	gem5::X86ISA::rw0
Bitfield< 19, 18 >	gem5::X86ISA::len0
Bitfield< 21, 20 >	gem5::X86ISA::rw1
Bitfield< 23, 22 >	gem5::X86ISA::len1
Bitfield< 25, 24 >	gem5::X86ISA::rw2
Bitfield< 27, 26 >	gem5::X86ISA::len2
Bitfield< 29, 28 >	gem5::X86ISA::rw3
Bitfield< 31, 30 >	gem5::X86ISA::len3
	gem5::X86ISA::vcnt
Bitfield< 8 >	gem5::X86ISA::fix
Bitfield< 10 >	gem5::X86ISA::wc
	gem5::X86ISA::targetCS
	gem5::X86ISA::targetESP
	gem5::X86ISA::targetEIP
	gem5::X86ISA::count
Bitfield< 8 >	gem5::X86ISA::MCGCP
Bitfield< 1 >	gem5::X86ISA::eipv
Bitfield< 2 >	gem5::X86ISA::mcip
Bitfield< 1 >	gem5::X86ISA::btf
Bitfield< 2 >	gem5::X86ISA::pb0
Bitfield< 3 >	gem5::X86ISA::pb1
Bitfield< 4 >	gem5::X86ISA::pb2
Bitfield< 5 >	gem5::X86ISA::pb3
	gem5::X86ISA::type
Bitfield< 51, 12 >	gem5::X86ISA::physbase
Bitfield< 51, 12 >	gem5::X86ISA::physmask
Bitfield< 10 >	gem5::X86ISA::fe
Bitfield< 11 >	gem5::X86ISA::e
	gem5::X86ISA::mcaErrorCode
Bitfield< 31, 16 >	gem5::X86ISA::modelSpecificCode
Bitfield< 56, 32 >	gem5::X86ISA::otherInfo
Bitfield< 57 >	gem5::X86ISA::pcc
Bitfield< 58 >	gem5::X86ISA::addrv
Bitfield< 59 >	gem5::X86ISA::miscv
Bitfield< 60 >	gem5::X86ISA::en
Bitfield< 61 >	gem5::X86ISA::uc
Bitfield< 62 >	gem5::X86ISA::over
Bitfield< 63 >	gem5::X86ISA::val
Bitfield< 8 >	gem5::X86ISA::lme
Bitfield< 10 >	gem5::X86ISA::lma
Bitfield< 11 >	gem5::X86ISA::nxe
Bitfield< 12 >	gem5::X86ISA::svme
Bitfield< 14 >	gem5::X86ISA::ffxsr
	gem5::X86ISA::targetEip
Bitfield< 47, 32 >	gem5::X86ISA::syscallCsAndSs
Bitfield< 63, 48 >	gem5::X86ISA::sysretCsAndSs
	gem5::X86ISA::mask
	gem5::X86ISA::eventMask
Bitfield< 15, 8 >	gem5::X86ISA::unitMask
Bitfield< 16 >	gem5::X86ISA::usr
Bitfield< 17 >	gem5::X86ISA::os
Bitfield< 19 >	gem5::X86ISA::pc
Bitfield< 20 >	gem5::X86ISA::intEn
Bitfield< 23 >	gem5::X86ISA::inv
Bitfield< 31, 24 >	gem5::X86ISA::counterMask
Bitfield< 19 >	gem5::X86ISA::mfdm
Bitfield< 20 >	gem5::X86ISA::mvdm
Bitfield< 21 >	gem5::X86ISA::tom2
Bitfield< 4 >	gem5::X86ISA::rd
	gem5::X86ISA::physAddr
Bitfield< 1 >	gem5::X86ISA::rInit
Bitfield< 2 >	gem5::X86ISA::disA20M
Bitfield< 1 >	gem5::X86ISA::enter
Bitfield< 2 >	gem5::X86ISA::smiCycle
Bitfield< 3 >	gem5::X86ISA::exit
Bitfield< 4 >	gem5::X86ISA::rsmCycle
	gem5::X86ISA::esi
Bitfield< 15, 3 >	gem5::X86ISA::si
Bitfield< 2 >	gem5::X86ISA::ti
Bitfield< 1, 0 >	gem5::X86ISA::rpl
	gem5::X86ISA::baseHigh
Bitfield< 39, 16 >	gem5::X86ISA::baseLow
Bitfield< 54 >	gem5::X86ISA::b
Bitfield< 53 >	gem5::X86ISA::l
Bitfield< 51, 48 >	gem5::X86ISA::limitHigh
Bitfield< 15, 0 >	gem5::X86ISA::limitLow
BitfieldType< SegDescriptorLimit >	gem5::X86ISA::limit
Bitfield< 46, 45 >	gem5::X86ISA::dpl
Bitfield< 44 >	gem5::X86ISA::s
Bitfield< 42 >	gem5::X86ISA::c
Bitfield< 41 >	gem5::X86ISA::r
Bitfield< 2 >	gem5::X86ISA::unusable
Bitfield< 3 >	gem5::X86ISA::defaultSize
Bitfield< 4 >	gem5::X86ISA::longMode
Bitfield< 6 >	gem5::X86ISA::granularity
Bitfield< 7 >	gem5::X86ISA::present
Bitfield< 12 >	gem5::X86ISA::writable
Bitfield< 13 >	gem5::X86ISA::readable
Bitfield< 14 >	gem5::X86ISA::expandDown
Bitfield< 15 >	gem5::X86ISA::system
	gem5::X86ISA::offsetHigh
Bitfield< 15, 0 >	gem5::X86ISA::offsetLow
Bitfield< 31, 16 >	gem5::X86ISA::selector
Bitfield< 35, 32 >	gem5::X86ISA::IST
	gem5::X86ISA::offset
Bitfield< 11 >	gem5::X86ISA::enable
Bitfield< 8 >	gem5::X86ISA::bsp